Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10CoveredT1,T6,T2 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10CoveredT1,T6,T2
11CoveredT1,T6,T2 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T6,T2
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 261734705 261732383 0 0
selKnown1 632442318 632439996 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 261734705 261732383 0 0
T1 1023199 1023196 0 0
T2 1115453 1115453 0 0
T5 38565 38562 0 0
T6 14963 14960 0 0
T16 26530 26527 0 0
T17 45662 45659 0 0
T18 9621 9618 0 0
T19 4877 4874 0 0
T20 2408 2405 0 0
T21 25605 25602 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 632442318 632439996 0 0
T1 2456391 2456388 0 0
T2 2679678 2679675 0 0
T5 92631 92628 0 0
T6 31986 31983 0 0
T16 63747 63744 0 0
T17 109662 109659 0 0
T18 17793 17790 0 0
T19 12108 12105 0 0
T20 5730 5727 0 0
T21 61689 61686 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 104779841 104779067 0 0
selKnown1 210814106 210813332 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 104779841 104779067 0 0
T1 409356 409355 0 0
T2 446453 446453 0 0
T5 15426 15425 0 0
T6 6444 6443 0 0
T16 10612 10611 0 0
T17 18265 18264 0 0
T18 4454 4453 0 0
T19 1951 1950 0 0
T20 982 981 0 0
T21 10242 10241 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 210814106 210813332 0 0
T1 818797 818796 0 0
T2 893226 893225 0 0
T5 30877 30876 0 0
T6 10662 10661 0 0
T16 21249 21248 0 0
T17 36554 36553 0 0
T18 5931 5930 0 0
T19 4036 4035 0 0
T20 1910 1909 0 0
T21 20563 20562 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10CoveredT1,T6,T2 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10CoveredT1,T6,T2
11CoveredT1,T6,T2 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T6,T2
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 104565362 104564588 0 0
selKnown1 210814106 210813332 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 104565362 104564588 0 0
T1 409168 409167 0 0
T2 445776 445776 0 0
T5 15426 15425 0 0
T6 5298 5297 0 0
T16 10612 10611 0 0
T17 18265 18264 0 0
T18 2940 2939 0 0
T19 1951 1950 0 0
T20 936 935 0 0
T21 10242 10241 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 210814106 210813332 0 0
T1 818797 818796 0 0
T2 893226 893225 0 0
T5 30877 30876 0 0
T6 10662 10661 0 0
T16 21249 21248 0 0
T17 36554 36553 0 0
T18 5931 5930 0 0
T19 4036 4035 0 0
T20 1910 1909 0 0
T21 20563 20562 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT5,T1,T6
01CoveredT5,T1,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT5,T1,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT5,T1,T6
11CoveredT5,T1,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 52389502 52388728 0 0
selKnown1 210814106 210813332 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 52389502 52388728 0 0
T1 204675 204674 0 0
T2 223224 223224 0 0
T5 7713 7712 0 0
T6 3221 3220 0 0
T16 5306 5305 0 0
T17 9132 9131 0 0
T18 2227 2226 0 0
T19 975 974 0 0
T20 490 489 0 0
T21 5121 5120 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 210814106 210813332 0 0
T1 818797 818796 0 0
T2 893226 893225 0 0
T5 30877 30876 0 0
T6 10662 10661 0 0
T16 21249 21248 0 0
T17 36554 36553 0 0
T18 5931 5930 0 0
T19 4036 4035 0 0
T20 1910 1909 0 0
T21 20563 20562 0 0

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