Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	72979289	9305762	0	62

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	9305762	0	62
T1	943779	129674	0	0
T2	454410	136931	0	0
T3	0	135502	0	0
T6	1776	0	0	0
T9	0	726014	0	0
T10	0	37007	0	1
T11	0	7285	0	1
T12	0	3827	0	1
T13	0	36114	0	1
T14	0	6933	0	1
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	0	0	0
T21	5140	567	0	1
T22	3281	0	0	0
T23	0	0	0	1
T24	0	0	0	1
T26	0	0	0	1
T135	0	0	0	1