Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	73917535	1760891	0	0
clk_enables_rd_A	73917535	12882	0	0
clk_hints_rd_A	73917535	11692	0	0
extclk_ctrl_rd_A	73917535	14629	0	0
extclk_ctrl_regwen_rd_A	73917535	10296	0	0
jitter_enable_rd_A	73917535	18349	0	0
jitter_regwen_rd_A	73917535	10832	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73917535	1760891	0	0
T2	454410	154564	0	0
T3	0	104301	0	0
T9	0	83877	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0
T25	0	101243	0	0
T27	181935	0	0	0
T56	0	228940	0	0
T73	0	49138	0	0
T74	0	34524	0	0
T75	0	110629	0	0
T76	0	121193	0	0
T77	0	62514	0	0
T78	881	0	0	0
T79	1226	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73917535	12882	0	0
T19	2018	1	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0
T27	181935	0	0	0
T78	881	0	0	0
T79	1226	0	0	0
T80	1368	0	0	0
T81	2092	0	0	0
T82	1929	0	0	0
T151	0	5	0	0
T152	0	2	0	0
T153	0	6	0	0
T154	0	9	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	10	0	0
T158	0	8	0	0
T159	0	7	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73917535	11692	0	0
T151	1879	6	0	0
T152	0	5	0	0
T153	0	1	0	0
T154	0	3	0	0
T156	0	8	0	0
T157	0	6	0	0
T158	0	3	0	0
T160	0	2	0	0
T161	0	6	0	0
T162	0	9	0	0
T163	2219	0	0	0
T164	1537	0	0	0
T165	1335	0	0	0
T166	1535	0	0	0
T167	1612	0	0	0
T168	2659	0	0	0
T169	907	0	0	0
T170	1072	0	0	0
T171	3060	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73917535	14629	0	0
T3	302366	0	0	0
T9	237175	0	0	0
T29	217975	0	0	0
T34	1047	0	0	0
T85	0	9	0	0
T87	0	49	0	0
T103	0	71	0	0
T117	1039	10	0	0
T128	1529	0	0	0
T129	2499	0	0	0
T130	1729	32	0	0
T131	1399	17	0	0
T172	984	7	0	0
T173	0	60	0	0
T174	0	48	0	0
T175	0	29	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73917535	10296	0	0
T106	1970	0	0	0
T176	22185	70	0	0
T177	0	29	0	0
T178	0	27	0	0
T179	0	21	0	0
T180	0	42	0	0
T181	0	966	0	0
T182	0	1398	0	0
T183	0	47	0	0
T184	0	2255	0	0
T185	0	41	0	0
T186	1300	0	0	0
T187	1213	0	0	0
T188	2360	0	0	0
T189	1669	0	0	0
T190	1128	0	0	0
T191	4516	0	0	0
T192	25745	0	0	0
T193	1124	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73917535	18349	0	0
T19	2018	94	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0
T27	181935	0	0	0
T78	881	0	0	0
T79	1226	0	0	0
T80	1368	0	0	0
T81	2092	0	0	0
T82	1929	0	0	0
T151	0	121	0	0
T152	0	102	0	0
T153	0	144	0	0
T154	0	130	0	0
T155	0	65	0	0
T156	0	52	0	0
T157	0	50	0	0
T160	0	59	0	0
T161	0	132	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73917535	10832	0	0
T61	0	251	0	0
T89	0	1	0	0
T91	0	6	0	0
T181	100325	1073	0	0
T182	0	1635	0	0
T184	0	2421	0	0
T194	0	1572	0	0
T195	0	1637	0	0
T196	0	21	0	0
T197	0	10	0	0
T198	12138	0	0	0
T199	939	0	0	0
T200	1593	0	0	0
T201	2397	0	0	0
T202	1716	0	0	0
T203	199771	0	0	0
T204	3304	0	0	0
T205	1631	0	0	0
T206	784	0	0	0