Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T6,T2

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	210814531	3030	0	0
g_div2.Div2Whole_A	210814531	3542	0	0
g_div4.Div4Stepped_A	104780243	2980	0	0
g_div4.Div4Whole_A	104780243	3406	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814531	3030	0	0
T1	818798	14	0	0
T2	893226	166	0	0
T3	0	64	0	0
T6	10663	15	0	0
T16	21249	0	0	0
T17	36555	0	0	0
T18	5931	3	0	0
T19	4036	0	0	0
T20	1910	3	0	0
T21	20563	0	0	0
T22	3151	0	0	0
T81	0	3	0	0
T117	0	2	0	0
T129	0	11	0	0
T130	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814531	3542	0	0
T1	818798	16	0	0
T2	893226	187	0	0
T3	0	73	0	0
T6	10663	15	0	0
T16	21249	0	0	0
T17	36555	0	0	0
T18	5931	7	0	0
T19	4036	0	0	0
T20	1910	4	0	0
T21	20563	0	0	0
T22	3151	0	0	0
T81	0	3	0	0
T82	0	1	0	0
T117	0	2	0	0
T128	0	2	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104780243	2980	0	0
T1	409356	11	0	0
T2	446453	166	0	0
T3	0	63	0	0
T6	6445	15	0	0
T16	10613	0	0	0
T17	18265	0	0	0
T18	4454	3	0	0
T19	1951	0	0	0
T20	982	3	0	0
T21	10242	0	0	0
T22	1556	0	0	0
T81	0	2	0	0
T117	0	2	0	0
T129	0	11	0	0
T130	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104780243	3406	0	0
T1	409356	13	0	0
T2	446453	187	0	0
T3	0	73	0	0
T6	6445	15	0	0
T16	10613	0	0	0
T17	18265	0	0	0
T18	4454	7	0	0
T19	1951	0	0	0
T20	982	3	0	0
T21	10242	0	0	0
T22	1556	0	0	0
T81	0	3	0	0
T82	0	1	0	0
T117	0	2	0	0
T128	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	210814531	3030	0	0
g_div2.Div2Whole_A	210814531	3542	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814531	3030	0	0
T1	818798	14	0	0
T2	893226	166	0	0
T3	0	64	0	0
T6	10663	15	0	0
T16	21249	0	0	0
T17	36555	0	0	0
T18	5931	3	0	0
T19	4036	0	0	0
T20	1910	3	0	0
T21	20563	0	0	0
T22	3151	0	0	0
T81	0	3	0	0
T117	0	2	0	0
T129	0	11	0	0
T130	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814531	3542	0	0
T1	818798	16	0	0
T2	893226	187	0	0
T3	0	73	0	0
T6	10663	15	0	0
T16	21249	0	0	0
T17	36555	0	0	0
T18	5931	7	0	0
T19	4036	0	0	0
T20	1910	4	0	0
T21	20563	0	0	0
T22	3151	0	0	0
T81	0	3	0	0
T82	0	1	0	0
T117	0	2	0	0
T128	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T6,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	104780243	2980	0	0
g_div4.Div4Whole_A	104780243	3406	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104780243	2980	0	0
T1	409356	11	0	0
T2	446453	166	0	0
T3	0	63	0	0
T6	6445	15	0	0
T16	10613	0	0	0
T17	18265	0	0	0
T18	4454	3	0	0
T19	1951	0	0	0
T20	982	3	0	0
T21	10242	0	0	0
T22	1556	0	0	0
T81	0	2	0	0
T117	0	2	0	0
T129	0	11	0	0
T130	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104780243	3406	0	0
T1	409356	13	0	0
T2	446453	187	0	0
T3	0	73	0	0
T6	6445	15	0	0
T16	10613	0	0	0
T17	18265	0	0	0
T18	4454	7	0	0
T19	1951	0	0	0
T20	982	3	0	0
T21	10242	0	0	0
T22	1556	0	0	0
T81	0	3	0	0
T82	0	1	0	0
T117	0	2	0	0
T128	0	2	0	0