Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	218937867	427	0	0
StatusRise_A	218937867	427	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218937867	427	0	0
T9	711525	0	0	0
T10	526263	0	0	0
T11	168378	0	0	0
T29	653925	0	0	0
T30	3147	0	0	0
T34	3141	4	0	0
T35	0	9	0	0
T36	0	11	0	0
T57	0	7	0	0
T131	4197	0	0	0
T170	0	9	0	0
T172	2952	0	0	0
T207	0	12	0	0
T208	0	7	0	0
T209	0	13	0	0
T210	0	4	0	0
T211	0	3	0	0
T212	5991	0	0	0
T213	7539	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218937867	427	0	0
T9	711525	0	0	0
T10	526263	0	0	0
T11	168378	0	0	0
T29	653925	0	0	0
T30	3147	0	0	0
T34	3141	4	0	0
T35	0	9	0	0
T36	0	11	0	0
T57	0	7	0	0
T131	4197	0	0	0
T170	0	9	0	0
T172	2952	0	0	0
T207	0	12	0	0
T208	0	7	0	0
T209	0	13	0	0
T210	0	4	0	0
T211	0	3	0	0
T212	5991	0	0	0
T213	7539	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72979289	142	0	0
StatusRise_A	72979289	142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	142	0	0
T9	237175	0	0	0
T10	175421	0	0	0
T11	56126	0	0	0
T29	217975	0	0	0
T30	1049	0	0	0
T34	1047	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	1399	0	0	0
T170	0	1	0	0
T172	984	0	0	0
T207	0	4	0	0
T208	0	3	0	0
T209	0	4	0	0
T210	0	2	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	2513	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	142	0	0
T9	237175	0	0	0
T10	175421	0	0	0
T11	56126	0	0	0
T29	217975	0	0	0
T30	1049	0	0	0
T34	1047	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	1399	0	0	0
T170	0	1	0	0
T172	984	0	0	0
T207	0	4	0	0
T208	0	3	0	0
T209	0	4	0	0
T210	0	2	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	2513	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72979289	131	0	0
StatusRise_A	72979289	131	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	131	0	0
T9	237175	0	0	0
T10	175421	0	0	0
T11	56126	0	0	0
T29	217975	0	0	0
T30	1049	0	0	0
T34	1047	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	1399	0	0	0
T170	0	3	0	0
T172	984	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	2513	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	131	0	0
T9	237175	0	0	0
T10	175421	0	0	0
T11	56126	0	0	0
T29	217975	0	0	0
T30	1049	0	0	0
T34	1047	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	1399	0	0	0
T170	0	3	0	0
T172	984	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	2513	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72979289	154	0	0
StatusRise_A	72979289	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	154	0	0
T9	237175	0	0	0
T10	175421	0	0	0
T11	56126	0	0	0
T29	217975	0	0	0
T30	1049	0	0	0
T34	1047	1	0	0
T35	0	4	0	0
T36	0	5	0	0
T57	0	3	0	0
T131	1399	0	0	0
T170	0	5	0	0
T172	984	0	0	0
T207	0	5	0	0
T208	0	2	0	0
T209	0	6	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	2513	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	154	0	0
T9	237175	0	0	0
T10	175421	0	0	0
T11	56126	0	0	0
T29	217975	0	0	0
T30	1049	0	0	0
T34	1047	1	0	0
T35	0	4	0	0
T36	0	5	0	0
T57	0	3	0	0
T131	1399	0	0	0
T170	0	5	0	0
T172	984	0	0	0
T207	0	5	0	0
T208	0	2	0	0
T209	0	6	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	2513	0	0	0