Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	30554	0	0
CgEnOn_A	2147483647	22670	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30554	0	0
T1	2393769	37	0	0
T2	2502976	561	0	0
T5	54016	3	0	0
T6	31434	3	0	0
T9	1945848	0	0	0
T10	378800	0	0	0
T11	224460	0	0	0
T16	59302	10	0	0
T17	108029	3	0	0
T18	18790	3	0	0
T19	11166	7	0	0
T20	5372	3	0	0
T21	57346	3	0	0
T22	3281	9	0	0
T29	354092	0	0	0
T30	4384	0	0	0
T34	4357	11	0	0
T35	0	10	0	0
T36	0	15	0	0
T57	0	10	0	0
T131	8433	0	0	0
T170	0	15	0	0
T172	12337	0	0	0
T207	0	15	0	0
T208	0	10	0	0
T209	0	15	0	0
T210	0	5	0	0
T211	0	5	0	0
T212	4209	0	0	0
T213	90392	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22670	0	0
T1	5714810	19	0	0
T2	5774725	528	0	0
T6	70086	0	0	0
T9	4261721	0	0	0
T10	813845	0	0	0
T11	482236	0	0	0
T16	136332	7	0	0
T17	264300	0	0	0
T18	40290	0	0	0
T19	25796	4	0	0
T20	12297	0	0	0
T21	131887	0	0	0
T22	20183	0	0	0
T29	862032	0	0	0
T30	9591	0	0	0
T34	9457	11	0	0
T35	0	10	0	0
T36	0	15	0	0
T57	0	10	0	0
T78	0	26	0	0
T79	0	35	0	0
T80	0	46	0	0
T83	0	14	0	0
T131	17805	0	0	0
T133	0	4	0	0
T170	0	15	0	0
T172	25195	0	0	0
T207	0	15	0	0
T208	0	10	0	0
T209	0	15	0	0
T210	0	5	0	0
T211	0	5	0	0
T212	9162	0	0	0
T213	194312	0	0	0
T214	0	3	0	0
T215	0	43	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104779841	134	0	0
CgEnOn_A	104779841	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104779841	134	0	0
T9	432483	0	0	0
T10	84160	0	0	0
T11	49871	0	0	0
T29	78673	0	0	0
T30	947	0	0	0
T34	951	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	1922	0	0	0
T170	0	3	0	0
T172	2945	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	918	0	0	0
T213	20067	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104779841	134	0	0
T9	432483	0	0	0
T10	84160	0	0	0
T11	49871	0	0	0
T29	78673	0	0	0
T30	947	0	0	0
T34	951	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	1922	0	0	0
T170	0	3	0	0
T172	2945	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	918	0	0	0
T213	20067	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	52389502	134	0	0
CgEnOn_A	52389502	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	134	0	0
T9	216240	0	0	0
T10	42080	0	0	0
T11	24936	0	0	0
T29	39336	0	0	0
T30	474	0	0	0
T34	475	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	961	0	0	0
T170	0	3	0	0
T172	1472	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	458	0	0	0
T213	10033	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	134	0	0
T9	216240	0	0	0
T10	42080	0	0	0
T11	24936	0	0	0
T29	39336	0	0	0
T30	474	0	0	0
T34	475	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	961	0	0	0
T170	0	3	0	0
T172	1472	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	458	0	0	0
T213	10033	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	52389502	134	0	0
CgEnOn_A	52389502	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	134	0	0
T9	216240	0	0	0
T10	42080	0	0	0
T11	24936	0	0	0
T29	39336	0	0	0
T30	474	0	0	0
T34	475	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	961	0	0	0
T170	0	3	0	0
T172	1472	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	458	0	0	0
T213	10033	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	134	0	0
T9	216240	0	0	0
T10	42080	0	0	0
T11	24936	0	0	0
T29	39336	0	0	0
T30	474	0	0	0
T34	475	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	961	0	0	0
T170	0	3	0	0
T172	1472	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	458	0	0	0
T213	10033	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	52389502	134	0	0
CgEnOn_A	52389502	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	134	0	0
T9	216240	0	0	0
T10	42080	0	0	0
T11	24936	0	0	0
T29	39336	0	0	0
T30	474	0	0	0
T34	475	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	961	0	0	0
T170	0	3	0	0
T172	1472	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	458	0	0	0
T213	10033	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	134	0	0
T9	216240	0	0	0
T10	42080	0	0	0
T11	24936	0	0	0
T29	39336	0	0	0
T30	474	0	0	0
T34	475	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	961	0	0	0
T170	0	3	0	0
T172	1472	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	458	0	0	0
T213	10033	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	210814106	134	0	0
CgEnOn_A	210814106	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814106	134	0	0
T9	864645	0	0	0
T10	168400	0	0	0
T11	99781	0	0	0
T29	157411	0	0	0
T30	2015	0	0	0
T34	1981	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	3628	0	0	0
T170	0	3	0	0
T172	4976	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	1917	0	0	0
T213	40226	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814106	132	0	0
T9	864645	0	0	0
T10	168400	0	0	0
T11	99781	0	0	0
T29	157411	0	0	0
T30	2015	0	0	0
T34	1981	2	0	0
T35	0	2	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	3628	0	0	0
T170	0	3	0	0
T172	4976	0	0	0
T207	0	3	0	0
T208	0	2	0	0
T209	0	3	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	1917	0	0	0
T213	40226	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	226332586	146	0	0
CgEnOn_A	226332586	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	146	0	0
T9	933701	0	0	0
T10	175421	0	0	0
T11	103942	0	0	0
T29	205975	0	0	0
T30	2100	0	0	0
T34	2077	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	3779	0	0	0
T170	0	1	0	0
T172	5185	0	0	0
T207	0	4	0	0
T208	0	3	0	0
T209	0	4	0	0
T210	0	2	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	41903	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	143	0	0
T9	933701	0	0	0
T10	175421	0	0	0
T11	103942	0	0	0
T29	205975	0	0	0
T30	2100	0	0	0
T34	2077	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	3779	0	0	0
T170	0	1	0	0
T172	5185	0	0	0
T207	0	4	0	0
T208	0	3	0	0
T209	0	4	0	0
T210	0	2	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	41903	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	226332586	146	0	0
CgEnOn_A	226332586	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	146	0	0
T9	933701	0	0	0
T10	175421	0	0	0
T11	103942	0	0	0
T29	205975	0	0	0
T30	2100	0	0	0
T34	2077	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	3779	0	0	0
T170	0	1	0	0
T172	5185	0	0	0
T207	0	4	0	0
T208	0	3	0	0
T209	0	4	0	0
T210	0	2	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	41903	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	143	0	0
T9	933701	0	0	0
T10	175421	0	0	0
T11	103942	0	0	0
T29	205975	0	0	0
T30	2100	0	0	0
T34	2077	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T57	0	2	0	0
T131	3779	0	0	0
T170	0	1	0	0
T172	5185	0	0	0
T207	0	4	0	0
T208	0	3	0	0
T209	0	4	0	0
T210	0	2	0	0
T211	0	1	0	0
T212	1997	0	0	0
T213	41903	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	108580202	155	0	0
CgEnOn_A	108580202	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108580202	155	0	0
T9	448471	0	0	0
T10	84203	0	0	0
T11	49892	0	0	0
T25	0	1	0	0
T29	95990	0	0	0
T30	1007	0	0	0
T34	946	1	0	0
T35	0	4	0	0
T36	0	5	0	0
T57	0	3	0	0
T131	1814	0	0	0
T170	0	5	0	0
T172	2488	0	0	0
T207	0	5	0	0
T208	0	2	0	0
T209	0	6	0	0
T210	0	1	0	0
T212	959	0	0	0
T213	20114	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108580202	155	0	0
T9	448471	0	0	0
T10	84203	0	0	0
T11	49892	0	0	0
T25	0	1	0	0
T29	95990	0	0	0
T30	1007	0	0	0
T34	946	1	0	0
T35	0	4	0	0
T36	0	5	0	0
T57	0	3	0	0
T131	1814	0	0	0
T170	0	5	0	0
T172	2488	0	0	0
T207	0	5	0	0
T208	0	2	0	0
T209	0	6	0	0
T210	0	1	0	0
T212	959	0	0	0
T213	20114	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	52389502	4806	0	0
CgEnOn_A	52389502	2841	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	4806	0	0
T1	204675	9	0	0
T2	223224	146	0	0
T5	7713	1	0	0
T6	3221	1	0	0
T16	5306	1	0	0
T17	9132	1	0	0
T18	2227	1	0	0
T19	975	2	0	0
T20	490	1	0	0
T21	5121	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389502	2841	0	0
T1	204675	3	0	0
T2	223224	135	0	0
T6	3221	0	0	0
T16	5306	0	0	0
T17	9132	0	0	0
T18	2227	0	0	0
T19	975	1	0	0
T20	490	0	0	0
T21	5121	0	0	0
T22	778	0	0	0
T78	0	9	0	0
T79	0	12	0	0
T80	0	16	0	0
T83	0	5	0	0
T133	0	1	0	0
T214	0	1	0	0
T215	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104779841	4795	0	0
CgEnOn_A	104779841	2830	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104779841	4795	0	0
T1	409356	9	0	0
T2	446453	147	0	0
T5	15426	1	0	0
T6	6444	1	0	0
T16	10612	1	0	0
T17	18265	1	0	0
T18	4454	1	0	0
T19	1951	2	0	0
T20	982	1	0	0
T21	10242	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104779841	2830	0	0
T1	409356	3	0	0
T2	446453	136	0	0
T6	6444	0	0	0
T16	10612	0	0	0
T17	18265	0	0	0
T18	4454	0	0	0
T19	1951	1	0	0
T20	982	0	0	0
T21	10242	0	0	0
T22	1556	0	0	0
T78	0	9	0	0
T79	0	12	0	0
T80	0	15	0	0
T83	0	4	0	0
T133	0	1	0	0
T214	0	1	0	0
T215	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	210814106	4782	0	0
CgEnOn_A	210814106	2815	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814106	4782	0	0
T1	818797	10	0	0
T2	893226	146	0	0
T5	30877	1	0	0
T6	10662	1	0	0
T16	21249	1	0	0
T17	36554	1	0	0
T18	5931	1	0	0
T19	4036	2	0	0
T20	1910	1	0	0
T21	20563	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814106	2815	0	0
T1	818797	4	0	0
T2	893226	135	0	0
T6	10662	0	0	0
T16	21249	0	0	0
T17	36554	0	0	0
T18	5931	0	0	0
T19	4036	1	0	0
T20	1910	0	0	0
T21	20563	0	0	0
T22	3150	0	0	0
T78	0	8	0	0
T79	0	11	0	0
T80	0	15	0	0
T83	0	5	0	0
T133	0	1	0	0
T214	0	1	0	0
T215	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	108580202	4827	0	0
CgEnOn_A	108580202	2860	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108580202	4827	0	0
T1	438218	10	0	0
T2	451530	147	0	0
T5	24079	1	0	0
T6	5331	1	0	0
T16	10625	1	0	0
T17	24037	1	0	0
T18	2966	1	0	0
T19	2018	2	0	0
T20	955	1	0	0
T21	10281	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108580202	2860	0	0
T1	438218	4	0	0
T2	451530	136	0	0
T6	5331	0	0	0
T16	10625	0	0	0
T17	24037	0	0	0
T18	2966	0	0	0
T19	2018	1	0	0
T20	955	0	0	0
T21	10281	0	0	0
T22	1575	0	0	0
T78	0	12	0	0
T79	0	11	0	0
T80	0	14	0	0
T83	0	5	0	0
T133	0	1	0	0
T214	0	1	0	0
T215	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T16,T2
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	226332586	2555	0	0
CgEnOn_A	226332586	2552	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2555	0	0
T1	960941	9	0	0
T2	940073	122	0	0
T3	0	78	0	0
T6	11107	0	0	0
T16	22135	7	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	9	0	0
T34	0	1	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2552	0	0
T1	960941	9	0	0
T2	940073	122	0	0
T3	0	78	0	0
T6	11107	0	0	0
T16	22135	7	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	9	0	0
T34	0	1	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T16,T2
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	226332586	2527	0	0
CgEnOn_A	226332586	2524	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2527	0	0
T1	960941	11	0	0
T2	940073	112	0	0
T3	0	63	0	0
T6	11107	0	0	0
T16	22135	6	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	8	0	0
T34	0	1	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2524	0	0
T1	960941	11	0	0
T2	940073	112	0	0
T3	0	63	0	0
T6	11107	0	0	0
T16	22135	6	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	8	0	0
T34	0	1	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T16,T2
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	226332586	2581	0	0
CgEnOn_A	226332586	2578	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2581	0	0
T1	960941	5	0	0
T2	940073	127	0	0
T3	0	79	0	0
T6	11107	0	0	0
T16	22135	8	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	11	0	0
T34	0	1	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2578	0	0
T1	960941	5	0	0
T2	940073	127	0	0
T3	0	79	0	0
T6	11107	0	0	0
T16	22135	8	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	11	0	0
T34	0	1	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T16,T2
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	226332586	2564	0	0
CgEnOn_A	226332586	2561	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2564	0	0
T1	960941	13	0	0
T2	940073	128	0	0
T3	0	69	0	0
T6	11107	0	0	0
T16	22135	7	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	9	0	0
T34	0	1	0	0
T132	0	5	0	0
T133	0	1	0	0
T134	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226332586	2561	0	0
T1	960941	13	0	0
T2	940073	128	0	0
T3	0	69	0	0
T6	11107	0	0	0
T16	22135	7	0	0
T17	44078	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21420	0	0	0
T22	3281	9	0	0
T34	0	1	0	0
T132	0	5	0	0
T133	0	1	0	0
T134	0	3	0	0