Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3886300

1

T4

20

T5

4

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1109999	1			T4	27		T5	5		T6	11
values[0x0]	1565598	1			T4	13		T5	1		T6	12
values[0x1]	1849852	1			T4	14		T5	6		T6	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342576	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4182873

1

T4

26

T5

7

T6

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17603	1			T2	1		T3	8		T23	1
valid_sources[0x01]	19179	1			T1	3		T2	11		T3	11
valid_sources[0x02]	18141	1			T1	1		T2	9		T3	10
valid_sources[0x03]	17970	1			T1	1		T2	3		T3	5
valid_sources[0x04]	17142	1			T6	1		T1	3		T2	3
valid_sources[0x05]	17391	1			T6	1		T1	1		T2	5
valid_sources[0x06]	17727	1			T1	1		T2	7		T3	10
valid_sources[0x07]	17781	1			T1	2		T2	3		T3	10
valid_sources[0x08]	16866	1			T1	2		T2	9		T3	10
valid_sources[0x09]	17525	1			T1	1		T3	9		T10	160
valid_sources[0x0a]	16245	1			T4	2		T2	6		T3	11
valid_sources[0x0b]	19126	1			T5	1		T1	1		T2	12
valid_sources[0x0c]	18284	1			T2	3		T3	4		T24	3
valid_sources[0x0d]	17395	1			T4	1		T1	1		T2	6
valid_sources[0x0e]	17687	1			T5	1		T1	1		T2	3
valid_sources[0x0f]	17090	1			T4	1		T1	1		T2	4
valid_sources[0x10]	20644	1			T1	1		T2	4		T3	9
valid_sources[0x11]	16591	1			T2	8		T3	10		T24	5
valid_sources[0x12]	16574	1			T1	1		T2	10		T3	7
valid_sources[0x13]	17011	1			T2	6		T3	16		T24	4
valid_sources[0x14]	17650	1			T1	1		T2	7		T3	7
valid_sources[0x15]	17556	1			T1	1		T2	4		T3	13
valid_sources[0x16]	18844	1			T2	4		T3	6		T10	424
valid_sources[0x17]	17729	1			T6	1		T2	6		T3	10
valid_sources[0x18]	17667	1			T2	5		T3	11		T24	7
valid_sources[0x19]	18335	1			T2	5		T3	12		T23	2
valid_sources[0x1a]	17613	1			T2	11		T3	10		T24	3
valid_sources[0x1b]	19267	1			T6	2		T1	7		T2	2
valid_sources[0x1c]	16456	1			T1	5		T2	6		T3	7
valid_sources[0x1d]	16935	1			T4	1		T6	1		T2	6
valid_sources[0x1e]	17782	1			T2	6		T3	11		T24	2
valid_sources[0x1f]	18269	1			T1	2		T2	1		T3	6
valid_sources[0x20]	17722	1			T6	1		T1	1		T2	8
valid_sources[0x21]	17648	1			T1	1		T2	10		T3	14
valid_sources[0x22]	18943	1			T4	2		T2	9		T3	9
valid_sources[0x23]	18515	1			T1	1		T2	1		T3	9
valid_sources[0x24]	16897	1			T6	1		T1	2		T2	18
valid_sources[0x25]	17160	1			T6	1		T2	4		T3	7
valid_sources[0x26]	17348	1			T1	9		T2	1		T3	14
valid_sources[0x27]	17597	1			T1	1		T2	5		T3	9
valid_sources[0x28]	16662	1			T1	2		T2	4		T3	9
valid_sources[0x29]	19119	1			T2	13		T3	8		T24	6
valid_sources[0x2a]	17308	1			T2	3		T3	6		T24	2
valid_sources[0x2b]	17608	1			T2	3		T3	10		T24	12
valid_sources[0x2c]	17466	1			T2	8		T3	7		T24	3
valid_sources[0x2d]	17798	1			T1	2		T2	7		T3	10
valid_sources[0x2e]	17629	1			T2	4		T3	7		T24	4
valid_sources[0x2f]	18895	1			T6	1		T2	5		T3	6
valid_sources[0x30]	16739	1			T2	4		T3	11		T24	2
valid_sources[0x31]	19106	1			T4	1		T2	8		T3	11
valid_sources[0x32]	18586	1			T2	4		T3	12		T24	1
valid_sources[0x33]	19162	1			T1	4		T2	8		T3	11
valid_sources[0x34]	17682	1			T1	1		T2	2		T3	7
valid_sources[0x35]	16987	1			T2	7		T3	5		T24	2
valid_sources[0x36]	16921	1			T6	1		T2	3		T3	7
valid_sources[0x37]	18808	1			T4	2		T2	12		T3	9
valid_sources[0x38]	17194	1			T1	1		T2	8		T3	10
valid_sources[0x39]	17128	1			T1	6		T2	8		T3	8
valid_sources[0x3a]	16959	1			T4	1		T1	2		T2	2
valid_sources[0x3b]	19831	1			T1	2		T2	4		T3	8
valid_sources[0x3c]	17776	1			T6	1		T2	4		T3	6
valid_sources[0x3d]	17185	1			T5	1		T1	2		T2	3
valid_sources[0x3e]	16492	1			T2	9		T3	8		T24	2
valid_sources[0x3f]	17678	1			T1	3		T2	6		T3	12
valid_sources[0x40]	17251	1			T4	1		T1	1		T2	3
valid_sources[0x41]	17916	1			T1	2		T2	9		T3	13
valid_sources[0x42]	17628	1			T5	1		T2	8		T3	13
valid_sources[0x43]	18272	1			T1	1		T2	1		T3	7
valid_sources[0x44]	17378	1			T1	3		T2	6		T3	7
valid_sources[0x45]	16916	1			T5	1		T2	6		T3	10
valid_sources[0x46]	18033	1			T2	3		T3	5		T24	2
valid_sources[0x47]	18429	1			T1	1		T2	8		T3	6
valid_sources[0x48]	18427	1			T6	1		T1	1		T2	12
valid_sources[0x49]	16009	1			T2	6		T3	8		T24	6
valid_sources[0x4a]	16175	1			T2	4		T3	7		T10	471
valid_sources[0x4b]	17817	1			T1	1		T2	5		T3	13
valid_sources[0x4c]	17789	1			T6	1		T2	7		T3	7
valid_sources[0x4d]	18372	1			T2	2		T3	13		T24	6
valid_sources[0x4e]	18308	1			T1	4		T2	8		T3	10
valid_sources[0x4f]	17275	1			T6	1		T2	5		T3	10
valid_sources[0x50]	18270	1			T2	3		T3	8		T24	2
valid_sources[0x51]	18116	1			T1	2		T2	3		T3	19
valid_sources[0x52]	16983	1			T1	1		T2	6		T3	8
valid_sources[0x53]	16316	1			T1	1		T2	3		T3	9
valid_sources[0x54]	18411	1			T1	2		T2	5		T3	4
valid_sources[0x55]	19037	1			T6	1		T2	8		T3	5
valid_sources[0x56]	17166	1			T1	3		T2	4		T3	9
valid_sources[0x57]	18297	1			T1	2		T2	5		T3	8
valid_sources[0x58]	17298	1			T3	10		T17	8		T24	2
valid_sources[0x59]	17254	1			T1	2		T2	5		T3	9
valid_sources[0x5a]	18348	1			T1	1		T2	2		T3	10
valid_sources[0x5b]	16796	1			T2	9		T3	5		T21	1
valid_sources[0x5c]	18074	1			T4	1		T2	2		T3	9
valid_sources[0x5d]	17866	1			T2	5		T3	10		T23	1
valid_sources[0x5e]	17503	1			T1	1		T2	10		T3	12
valid_sources[0x5f]	17220	1			T1	1		T2	3		T3	10
valid_sources[0x60]	16536	1			T1	3		T2	4		T3	9
valid_sources[0x61]	16853	1			T2	3		T3	8		T24	2
valid_sources[0x62]	18070	1			T1	4		T2	2		T3	12
valid_sources[0x63]	18668	1			T1	1		T2	11		T3	8
valid_sources[0x64]	17533	1			T1	3		T2	7		T3	5
valid_sources[0x65]	17242	1			T2	9		T3	9		T24	3
valid_sources[0x66]	17421	1			T6	1		T2	3		T3	8
valid_sources[0x67]	17971	1			T5	1		T2	3		T3	10
valid_sources[0x68]	16762	1			T2	5		T3	7		T10	17
valid_sources[0x69]	16457	1			T1	1		T2	8		T3	8
valid_sources[0x6a]	18072	1			T6	1		T2	8		T3	10
valid_sources[0x6b]	17443	1			T2	4		T3	12		T23	1
valid_sources[0x6c]	17607	1			T5	1		T1	1		T2	5
valid_sources[0x6d]	18838	1			T1	1		T2	3		T3	16
valid_sources[0x6e]	18192	1			T1	1		T2	4		T3	7
valid_sources[0x6f]	16998	1			T1	2		T2	3		T3	4
valid_sources[0x70]	18083	1			T6	1		T2	6		T3	9
valid_sources[0x71]	19129	1			T1	2		T2	10		T3	9
valid_sources[0x72]	17693	1			T2	5		T3	8		T21	1
valid_sources[0x73]	19468	1			T1	6		T2	8		T3	11
valid_sources[0x74]	17802	1			T4	4		T5	1		T2	16
valid_sources[0x75]	16582	1			T1	5		T2	11		T3	9
valid_sources[0x76]	17455	1			T2	13		T3	10		T24	2
valid_sources[0x77]	17893	1			T1	2		T2	4		T3	10
valid_sources[0x78]	17903	1			T2	9		T3	11		T24	2
valid_sources[0x79]	19608	1			T6	1		T1	3		T2	6
valid_sources[0x7a]	20152	1			T4	3		T2	9		T3	13
valid_sources[0x7b]	18039	1			T1	4		T2	1		T3	9
valid_sources[0x7c]	16418	1			T4	1		T1	2		T2	5
valid_sources[0x7d]	16735	1			T6	1		T1	5		T2	2
valid_sources[0x7e]	17621	1			T4	2		T1	2		T2	3
valid_sources[0x7f]	17294	1			T1	3		T2	5		T3	11
valid_sources[0x80]	18296	1			T1	2		T2	7		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

980347

1

T4

13

T5

3

T6

3

values[0x0]

all_enables

biggest_size

1473980

1

T4

5

T6

3

T1

81

values[0x1]

all_enables

biggest_size

1431973

1

T4

2

T5

1

T6

1