Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T17
0	1	Covered	T2,T3,T193
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T18,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	836339713	11953	0	0
GateOpen_A	836339713	18575	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	836339713	11953	0	0
T2	1252590	34	0	0
T3	1728648	74	0	0
T10	0	66	0	0
T11	0	184	0	0
T12	0	44	0	0
T17	13286	4	0	0
T18	6027	21	0	0
T19	6798	0	0	0
T20	5284	0	0	0
T21	8222	0	0	0
T22	22215	0	0	0
T23	43635	0	0	0
T27	5310	0	0	0
T75	0	28	0	0
T81	0	4	0	0
T104	0	25	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	836339713	18575	0	0
T1	327295	4	0	0
T2	1252590	46	0	0
T3	1728648	90	0	0
T4	16877	4	0	0
T5	9888	0	0	0
T6	8666	4	0	0
T17	13286	4	0	0
T18	6027	25	0	0
T19	6798	4	0	0
T20	5284	4	0	0
T22	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T17
0	1	Covered	T2,T3,T193
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T18,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	92043563	2816	0	0
GateOpen_A	92043563	4471	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043563	2816	0	0
T2	133457	7	0	0
T3	190681	15	0	0
T10	0	16	0	0
T11	0	38	0	0
T12	0	12	0	0
T17	1456	1	0	0
T18	666	6	0	0
T19	803	0	0	0
T20	577	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5089	0	0	0
T27	594	0	0	0
T75	0	7	0	0
T81	0	1	0	0
T104	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043563	4471	0	0
T1	36355	1	0	0
T2	133457	10	0	0
T3	190681	19	0	0
T4	2080	1	0	0
T5	1129	0	0	0
T6	1024	1	0	0
T17	1456	1	0	0
T18	666	7	0	0
T19	803	1	0	0
T20	577	1	0	0
T22	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T17
0	1	Covered	T2,T3,T193
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T18,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	184087956	3059	0	0
GateOpen_A	184087956	4714	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184087956	3059	0	0
T2	266913	11	0	0
T3	381363	19	0	0
T10	0	18	0	0
T11	0	51	0	0
T12	0	11	0	0
T17	2912	1	0	0
T18	1331	6	0	0
T19	1606	0	0	0
T20	1153	0	0	0
T21	1930	0	0	0
T22	3133	0	0	0
T23	10177	0	0	0
T27	1188	0	0	0
T75	0	8	0	0
T81	0	1	0	0
T104	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184087956	4714	0	0
T1	72710	1	0	0
T2	266913	14	0	0
T3	381363	23	0	0
T4	4160	1	0	0
T5	2258	0	0	0
T6	2047	1	0	0
T17	2912	1	0	0
T18	1331	7	0	0
T19	1606	1	0	0
T20	1153	1	0	0
T22	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T17
0	1	Covered	T2,T3,T193
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T18,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	369735539	3025	0	0
GateOpen_A	369735539	4681	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735539	3025	0	0
T2	533578	8	0	0
T3	763377	19	0	0
T10	0	16	0	0
T11	0	49	0	0
T12	0	11	0	0
T17	5945	1	0	0
T18	2715	6	0	0
T19	2926	0	0	0
T20	2369	0	0	0
T21	3552	0	0	0
T22	11677	0	0	0
T23	18912	0	0	0
T27	2352	0	0	0
T75	0	6	0	0
T81	0	1	0	0
T104	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735539	4681	0	0
T1	145484	1	0	0
T2	533578	11	0	0
T3	763377	23	0	0
T4	7091	1	0	0
T5	4334	0	0	0
T6	3730	1	0	0
T17	5945	1	0	0
T18	2715	7	0	0
T19	2926	1	0	0
T20	2369	1	0	0
T22	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T17
0	1	Covered	T2,T3,T193
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T18,T36,T37
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	190472655	3053	0	0
GateOpen_A	190472655	4709	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190472655	3053	0	0
T2	318642	8	0	0
T3	393227	21	0	0
T10	0	16	0	0
T11	0	46	0	0
T12	0	10	0	0
T17	2973	1	0	0
T18	1315	3	0	0
T19	1463	0	0	0
T20	1185	0	0	0
T21	1776	0	0	0
T22	5839	0	0	0
T23	9457	0	0	0
T27	1176	0	0	0
T75	0	7	0	0
T81	0	1	0	0
T104	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190472655	4709	0	0
T1	72746	1	0	0
T2	318642	11	0	0
T3	393227	25	0	0
T4	3546	1	0	0
T5	2167	0	0	0
T6	1865	1	0	0
T17	2973	1	0	0
T18	1315	4	0	0
T19	1463	1	0	0
T20	1185	1	0	0
T22	0	2	0	0