Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	820798470	72721	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	820798470	72721	0	0
T1	757750	205	0	0
T2	810985	133	0	0
T3	3516210	365	0	0
T10	0	383	0	0
T11	0	1721	0	0
T12	0	286	0	0
T13	0	225	0	0
T14	0	149	0	0
T15	0	2218	0	0
T16	0	981	0	0
T17	7425	0	0	0
T18	7565	0	0	0
T19	14625	0	0	0
T20	6165	0	0	0
T21	9245	0	0	0
T22	23105	0	0	0
T23	5905	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164159694	10465	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	10465	0	0
T1	151550	26	0	0
T2	162197	21	0	0
T3	703242	50	0	0
T10	0	55	0	0
T11	0	219	0	0
T12	0	44	0	0
T13	0	30	0	0
T14	0	23	0	0
T15	0	289	0	0
T16	0	129	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164159694	10381	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	10381	0	0
T1	151550	30	0	0
T2	162197	21	0	0
T3	703242	47	0	0
T10	0	55	0	0
T11	0	251	0	0
T12	0	44	0	0
T13	0	31	0	0
T14	0	22	0	0
T15	0	281	0	0
T16	0	125	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164159694	14619	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	14619	0	0
T1	151550	39	0	0
T2	162197	27	0	0
T3	703242	72	0	0
T10	0	77	0	0
T11	0	342	0	0
T12	0	59	0	0
T13	0	45	0	0
T14	0	30	0	0
T15	0	455	0	0
T16	0	196	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164159694	14631	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	14631	0	0
T1	151550	43	0	0
T2	162197	27	0	0
T3	703242	74	0	0
T10	0	78	0	0
T11	0	340	0	0
T12	0	58	0	0
T13	0	46	0	0
T14	0	31	0	0
T15	0	448	0	0
T16	0	201	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	164159694	22625	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	22625	0	0
T1	151550	67	0	0
T2	162197	37	0	0
T3	703242	122	0	0
T10	0	118	0	0
T11	0	569	0	0
T12	0	81	0	0
T13	0	73	0	0
T14	0	43	0	0
T15	0	745	0	0
T16	0	330	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0