Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T3,T22

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	164159694	161414747	0	0
AllClkBypReqTrue_A	164159694	124429	0	0
IoClkBypReqFalse_A	164159694	161333812	0	2409
IoClkBypReqTrue_A	164159694	200806	0	0
LcClkBypAckFalse_A	164159694	161420838	0	0
LcClkBypAckTrue_A	164159694	118338	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	161414747	0	0
T1	151550	151451	0	0
T2	162197	161967	0	0
T3	703242	701409	0	0
T4	1846	1500	0	0
T5	767	729	0	0
T6	1865	1769	0	0
T17	1485	1444	0	0
T18	1513	1459	0	0
T19	2925	2252	0	0
T20	1233	1034	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	124429	0	0
T1	151550	0	0	0
T2	162197	84	0	0
T3	703242	190	0	0
T4	1846	310	0	0
T5	767	20	0	0
T6	1865	0	0	0
T10	0	584	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	482	0	0
T20	1233	64	0	0
T77	0	232	0	0
T107	0	375	0	0
T117	0	348	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	161333812	0	2409
T1	151550	151449	0	3
T2	162197	161865	0	3
T3	703242	701061	0	3
T4	1846	1399	0	3
T5	767	706	0	3
T6	1865	1399	0	3
T17	1485	1442	0	3
T18	1513	1457	0	3
T19	2925	2194	0	3
T20	1233	1018	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	200806	0	0
T1	151550	0	0	0
T2	162197	178	0	0
T3	703242	516	0	0
T4	1846	409	0	0
T5	767	41	0	0
T6	1865	368	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	538	0	0
T20	1233	78	0	0
T21	0	434	0	0
T23	0	225	0	0
T27	0	291	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	161420838	0	0
T1	151550	151451	0	0
T2	162197	161931	0	0
T3	703242	701251	0	0
T4	1846	1609	0	0
T5	767	749	0	0
T6	1865	1541	0	0
T17	1485	1444	0	0
T18	1513	1459	0	0
T19	2925	2448	0	0
T20	1233	1062	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	118338	0	0
T1	151550	0	0	0
T2	162197	120	0	0
T3	703242	348	0	0
T4	1846	201	0	0
T5	767	0	0	0
T6	1865	228	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	286	0	0
T20	1233	36	0	0
T21	0	178	0	0
T23	0	81	0	0
T27	0	127	0	0
T107	0	180	0	0