Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1585737392	13991	0	0
TransStop_A	1585737392	7199	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585737392	13991	0	0
T2	2511316	53	0	0
T3	3228840	57	0	0
T10	0	102	0	0
T11	0	143	0	0
T12	0	61	0	0
T17	24768	4	0	0
T18	11120	0	0	0
T19	12192	0	0	0
T20	9876	0	0	0
T21	14800	0	0	0
T22	48656	0	0	0
T23	78804	0	0	0
T27	9800	0	0	0
T76	0	18	0	0
T81	0	4	0	0
T84	0	64	0	0
T118	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1585737392	7199	0	0
T2	2511316	29	0	0
T3	3228840	24	0	0
T10	0	46	0	0
T11	0	89	0	0
T12	0	33	0	0
T17	24768	4	0	0
T18	11120	0	0	0
T19	12192	0	0	0
T20	9876	0	0	0
T21	14800	0	0	0
T22	48656	0	0	0
T23	78804	0	0	0
T27	9800	0	0	0
T76	0	12	0	0
T81	0	4	0	0
T84	0	35	0	0
T118	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	396434348	3499	0	0
TransStop_A	396434348	1806	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	3499	0	0
T2	627829	13	0	0
T3	807210	15	0	0
T10	0	26	0	0
T11	0	34	0	0
T12	0	14	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	2	0	0
T81	0	1	0	0
T84	0	17	0	0
T118	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	1806	0	0
T2	627829	6	0	0
T3	807210	8	0	0
T10	0	14	0	0
T11	0	22	0	0
T12	0	7	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	2	0	0
T81	0	1	0	0
T84	0	8	0	0
T118	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	396434348	3514	0	0
TransStop_A	396434348	1808	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	3514	0	0
T2	627829	12	0	0
T3	807210	14	0	0
T10	0	19	0	0
T11	0	40	0	0
T12	0	17	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	5	0	0
T81	0	1	0	0
T84	0	18	0	0
T118	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	1808	0	0
T2	627829	7	0	0
T3	807210	4	0	0
T10	0	9	0	0
T11	0	25	0	0
T12	0	10	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	3	0	0
T81	0	1	0	0
T84	0	10	0	0
T118	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	396434348	3435	0	0
TransStop_A	396434348	1779	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	3435	0	0
T2	627829	13	0	0
T3	807210	14	0	0
T10	0	28	0	0
T11	0	32	0	0
T12	0	14	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	5	0	0
T81	0	1	0	0
T84	0	12	0	0
T118	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	1779	0	0
T2	627829	7	0	0
T3	807210	6	0	0
T10	0	12	0	0
T11	0	19	0	0
T12	0	7	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	3	0	0
T81	0	1	0	0
T84	0	6	0	0
T118	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	396434348	3543	0	0
TransStop_A	396434348	1806	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	3543	0	0
T2	627829	15	0	0
T3	807210	14	0	0
T10	0	29	0	0
T11	0	37	0	0
T12	0	16	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	6	0	0
T81	0	1	0	0
T84	0	17	0	0
T118	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396434348	1806	0	0
T2	627829	9	0	0
T3	807210	6	0	0
T10	0	11	0	0
T11	0	23	0	0
T12	0	9	0	0
T17	6192	1	0	0
T18	2780	0	0	0
T19	3048	0	0	0
T20	2469	0	0	0
T21	3700	0	0	0
T22	12164	0	0	0
T23	19701	0	0	0
T27	2450	0	0	0
T76	0	4	0	0
T81	0	1	0	0
T84	0	11	0	0
T118	0	1	0	0