Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	164159694	18375927	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	18375927	0	57
T1	151550	25161	0	1
T2	162197	10067	0	0
T3	703242	42191	0	0
T10	0	38673	0	0
T11	0	204106	0	0
T12	0	21641	0	0
T13	0	25297	0	1
T14	0	12794	0	1
T15	0	104043	0	0
T17	1485	0	0	0
T18	1513	0	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0
T25	0	661	0	1
T119	0	0	0	1
T120	0	0	0	1
T121	0	0	0	1
T122	0	0	0	1
T123	0	0	0	1
T124	0	0	0	1