Assert Coverage for Module :
clkmgr_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165096631 |
5743995 |
0 |
0 |
T10 |
123639 |
55109 |
0 |
0 |
T11 |
0 |
146236 |
0 |
0 |
T15 |
0 |
211956 |
0 |
0 |
T16 |
0 |
150606 |
0 |
0 |
T26 |
0 |
17795 |
0 |
0 |
T29 |
108518 |
0 |
0 |
0 |
T31 |
1807 |
0 |
0 |
0 |
T33 |
0 |
128315 |
0 |
0 |
T71 |
0 |
65256 |
0 |
0 |
T72 |
0 |
124336 |
0 |
0 |
T73 |
0 |
47750 |
0 |
0 |
T74 |
0 |
82540 |
0 |
0 |
T75 |
1567 |
0 |
0 |
0 |
T76 |
2267 |
0 |
0 |
0 |
T77 |
2095 |
0 |
0 |
0 |
T78 |
1284 |
0 |
0 |
0 |
T79 |
2350 |
0 |
0 |
0 |
T80 |
2700 |
0 |
0 |
0 |
T81 |
1670 |
0 |
0 |
0 |
clk_enables_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165096631 |
33126 |
0 |
0 |
T26 |
0 |
691 |
0 |
0 |
T37 |
1106 |
0 |
0 |
0 |
T141 |
2252 |
5 |
0 |
0 |
T142 |
1752 |
6 |
0 |
0 |
T143 |
0 |
1 |
0 |
0 |
T144 |
0 |
4 |
0 |
0 |
T145 |
0 |
15 |
0 |
0 |
T146 |
0 |
4 |
0 |
0 |
T147 |
0 |
2 |
0 |
0 |
T148 |
0 |
3 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T150 |
32577 |
0 |
0 |
0 |
T151 |
89600 |
0 |
0 |
0 |
T152 |
2185 |
0 |
0 |
0 |
T153 |
972 |
0 |
0 |
0 |
T154 |
1473 |
0 |
0 |
0 |
T155 |
32417 |
0 |
0 |
0 |
T156 |
1423 |
0 |
0 |
0 |
clk_hints_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165096631 |
29596 |
0 |
0 |
T16 |
328413 |
0 |
0 |
0 |
T26 |
581149 |
516 |
0 |
0 |
T43 |
0 |
28 |
0 |
0 |
T116 |
0 |
2 |
0 |
0 |
T119 |
88139 |
0 |
0 |
0 |
T143 |
2160 |
6 |
0 |
0 |
T145 |
0 |
9 |
0 |
0 |
T146 |
0 |
5 |
0 |
0 |
T147 |
0 |
4 |
0 |
0 |
T148 |
0 |
5 |
0 |
0 |
T149 |
0 |
1 |
0 |
0 |
T157 |
0 |
1900 |
0 |
0 |
T158 |
2494 |
0 |
0 |
0 |
T159 |
102984 |
0 |
0 |
0 |
T160 |
1694 |
0 |
0 |
0 |
T161 |
3753 |
0 |
0 |
0 |
T162 |
17047 |
0 |
0 |
0 |
T163 |
1077 |
0 |
0 |
0 |
extclk_ctrl_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165096631 |
37654 |
0 |
0 |
T1 |
151550 |
0 |
0 |
0 |
T2 |
162197 |
0 |
0 |
0 |
T3 |
703242 |
0 |
0 |
0 |
T4 |
1846 |
40 |
0 |
0 |
T5 |
767 |
2 |
0 |
0 |
T6 |
1865 |
31 |
0 |
0 |
T17 |
1485 |
0 |
0 |
0 |
T18 |
1513 |
0 |
0 |
0 |
T19 |
2925 |
0 |
0 |
0 |
T20 |
1233 |
0 |
0 |
0 |
T21 |
0 |
28 |
0 |
0 |
T38 |
0 |
21 |
0 |
0 |
T77 |
0 |
32 |
0 |
0 |
T80 |
0 |
48 |
0 |
0 |
T107 |
0 |
76 |
0 |
0 |
T117 |
0 |
49 |
0 |
0 |
T152 |
0 |
76 |
0 |
0 |
extclk_ctrl_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165096631 |
28131 |
0 |
0 |
T15 |
435229 |
0 |
0 |
0 |
T26 |
0 |
575 |
0 |
0 |
T34 |
0 |
1007 |
0 |
0 |
T37 |
1106 |
0 |
0 |
0 |
T115 |
0 |
25 |
0 |
0 |
T155 |
32417 |
46 |
0 |
0 |
T156 |
1423 |
0 |
0 |
0 |
T157 |
0 |
2139 |
0 |
0 |
T164 |
0 |
63 |
0 |
0 |
T165 |
0 |
39 |
0 |
0 |
T166 |
0 |
3374 |
0 |
0 |
T167 |
0 |
67 |
0 |
0 |
T168 |
0 |
11 |
0 |
0 |
T169 |
2021 |
0 |
0 |
0 |
T170 |
3439 |
0 |
0 |
0 |
T171 |
1413 |
0 |
0 |
0 |
T172 |
1121 |
0 |
0 |
0 |
T173 |
2240 |
0 |
0 |
0 |
T174 |
2069 |
0 |
0 |
0 |
jitter_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165096631 |
38640 |
0 |
0 |
T26 |
0 |
771 |
0 |
0 |
T37 |
1106 |
0 |
0 |
0 |
T116 |
0 |
111 |
0 |
0 |
T141 |
2252 |
65 |
0 |
0 |
T142 |
1752 |
53 |
0 |
0 |
T143 |
0 |
100 |
0 |
0 |
T144 |
0 |
135 |
0 |
0 |
T145 |
0 |
219 |
0 |
0 |
T146 |
0 |
227 |
0 |
0 |
T147 |
0 |
257 |
0 |
0 |
T148 |
0 |
78 |
0 |
0 |
T150 |
32577 |
0 |
0 |
0 |
T151 |
89600 |
0 |
0 |
0 |
T152 |
2185 |
0 |
0 |
0 |
T153 |
972 |
0 |
0 |
0 |
T154 |
1473 |
0 |
0 |
0 |
T155 |
32417 |
0 |
0 |
0 |
T156 |
1423 |
0 |
0 |
0 |
jitter_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
165096631 |
31405 |
0 |
0 |
T26 |
581149 |
693 |
0 |
0 |
T34 |
0 |
1049 |
0 |
0 |
T119 |
88139 |
0 |
0 |
0 |
T120 |
6641 |
0 |
0 |
0 |
T157 |
0 |
2463 |
0 |
0 |
T161 |
3753 |
0 |
0 |
0 |
T162 |
17047 |
0 |
0 |
0 |
T163 |
1077 |
0 |
0 |
0 |
T166 |
0 |
4038 |
0 |
0 |
T175 |
0 |
4744 |
0 |
0 |
T176 |
0 |
2505 |
0 |
0 |
T177 |
0 |
4158 |
0 |
0 |
T178 |
0 |
2563 |
0 |
0 |
T179 |
0 |
974 |
0 |
0 |
T180 |
0 |
1574 |
0 |
0 |
T181 |
1488 |
0 |
0 |
0 |
T182 |
968 |
0 |
0 |
0 |
T183 |
2278 |
0 |
0 |
0 |
T184 |
1432 |
0 |
0 |
0 |