Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	492479082	426	0	0
StatusRise_A	492479082	426	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492479082	426	0	0
T18	4539	14	0	0
T19	8775	0	0	0
T20	3699	0	0	0
T21	5547	0	0	0
T22	13863	0	0	0
T23	3543	0	0	0
T24	336294	0	0	0
T27	7131	0	0	0
T36	0	7	0	0
T37	0	8	0	0
T38	4851	0	0	0
T48	0	5	0	0
T107	8292	0	0	0
T185	0	5	0	0
T186	0	11	0	0
T187	0	11	0	0
T188	0	2	0	0
T189	0	14	0	0
T190	0	13	0	0
T191	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492479082	426	0	0
T18	4539	14	0	0
T19	8775	0	0	0
T20	3699	0	0	0
T21	5547	0	0	0
T22	13863	0	0	0
T23	3543	0	0	0
T24	336294	0	0	0
T27	7131	0	0	0
T36	0	7	0	0
T37	0	8	0	0
T38	4851	0	0	0
T48	0	5	0	0
T107	8292	0	0	0
T185	0	5	0	0
T186	0	11	0	0
T187	0	11	0	0
T188	0	2	0	0
T189	0	14	0	0
T190	0	13	0	0
T191	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	164159694	144	0	0
StatusRise_A	164159694	144	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	144	0	0
T18	1513	5	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0
T24	112098	0	0	0
T27	2377	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	1617	0	0	0
T48	0	1	0	0
T107	2764	0	0	0
T185	0	3	0	0
T186	0	4	0	0
T187	0	2	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	144	0	0
T18	1513	5	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0
T24	112098	0	0	0
T27	2377	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	1617	0	0	0
T48	0	1	0	0
T107	2764	0	0	0
T185	0	3	0	0
T186	0	4	0	0
T187	0	2	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	164159694	143	0	0
StatusRise_A	164159694	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	143	0	0
T18	1513	6	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0
T24	112098	0	0	0
T27	2377	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	1617	0	0	0
T48	0	2	0	0
T107	2764	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T191	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	143	0	0
T18	1513	6	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0
T24	112098	0	0	0
T27	2377	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	1617	0	0	0
T48	0	2	0	0
T107	2764	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T191	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	164159694	139	0	0
StatusRise_A	164159694	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	139	0	0
T18	1513	3	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0
T24	112098	0	0	0
T27	2377	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	1617	0	0	0
T48	0	2	0	0
T107	2764	0	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	5	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164159694	139	0	0
T18	1513	3	0	0
T19	2925	0	0	0
T20	1233	0	0	0
T21	1849	0	0	0
T22	4621	0	0	0
T23	1181	0	0	0
T24	112098	0	0	0
T27	2377	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	1617	0	0	0
T48	0	2	0	0
T107	2764	0	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	5	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	4	0	0