Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	43416	0	0
CgEnOn_A	2147483647	34310	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43416	0	0
T1	327293	3	0	0
T2	3763903	68	0	0
T3	4957487	136	0	0
T4	16874	3	0	0
T5	9886	3	0	0
T6	8663	3	0	0
T10	0	26	0	0
T17	38052	7	0	0
T18	30054	56	0	0
T19	33476	3	0	0
T20	26524	3	0	0
T21	32349	0	0	0
T22	98324	0	0	0
T23	172008	0	0	0
T24	479337	0	0	0
T27	21195	0	0	0
T36	0	10	0	0
T37	0	20	0	0
T38	8152	0	0	0
T48	0	10	0	0
T76	0	2	0	0
T107	13668	0	0	0
T185	0	5	0	0
T186	0	20	0	0
T187	0	20	0	0
T189	0	20	0	0
T190	0	20	0	0
T192	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34310	0	0
T2	3763903	56	0	0
T3	4957487	103	0	0
T10	0	106	0	0
T11	0	236	0	0
T17	38052	4	0	0
T18	30054	53	0	0
T19	33476	0	0	0
T20	26524	0	0	0
T21	40570	0	0	0
T22	120538	0	0	0
T23	215640	0	0	0
T24	479337	0	0	0
T27	26504	0	0	0
T36	0	10	0	0
T37	0	20	0	0
T38	8152	0	0	0
T48	0	10	0	0
T75	0	30	0	0
T76	0	2	0	0
T81	0	4	0	0
T104	0	27	0	0
T107	13668	0	0	0
T185	0	5	0	0
T186	0	20	0	0
T187	0	20	0	0
T189	0	20	0	0
T190	0	20	0	0
T191	0	2	0	0
T192	0	4	0	0
T193	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	184087578	149	0	0
CgEnOn_A	184087578	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184087578	149	0	0
T18	1331	6	0	0
T19	1606	0	0	0
T20	1153	0	0	0
T21	1930	0	0	0
T22	3132	0	0	0
T23	10177	0	0	0
T24	31055	0	0	0
T27	1188	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	868	0	0	0
T48	0	2	0	0
T107	1548	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184087578	149	0	0
T18	1331	6	0	0
T19	1606	0	0	0
T20	1153	0	0	0
T21	1930	0	0	0
T22	3132	0	0	0
T23	10177	0	0	0
T24	31055	0	0	0
T27	1188	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	868	0	0	0
T48	0	2	0	0
T107	1548	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	92043185	149	0	0
CgEnOn_A	92043185	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	149	0	0
T18	665	6	0	0
T19	802	0	0	0
T20	576	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5088	0	0	0
T24	15528	0	0	0
T27	593	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	433	0	0	0
T48	0	2	0	0
T107	772	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	149	0	0
T18	665	6	0	0
T19	802	0	0	0
T20	576	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5088	0	0	0
T24	15528	0	0	0
T27	593	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	433	0	0	0
T48	0	2	0	0
T107	772	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	92043185	149	0	0
CgEnOn_A	92043185	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	149	0	0
T18	665	6	0	0
T19	802	0	0	0
T20	576	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5088	0	0	0
T24	15528	0	0	0
T27	593	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	433	0	0	0
T48	0	2	0	0
T107	772	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	149	0	0
T18	665	6	0	0
T19	802	0	0	0
T20	576	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5088	0	0	0
T24	15528	0	0	0
T27	593	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	433	0	0	0
T48	0	2	0	0
T107	772	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	92043185	149	0	0
CgEnOn_A	92043185	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	149	0	0
T18	665	6	0	0
T19	802	0	0	0
T20	576	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5088	0	0	0
T24	15528	0	0	0
T27	593	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	433	0	0	0
T48	0	2	0	0
T107	772	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	149	0	0
T18	665	6	0	0
T19	802	0	0	0
T20	576	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5088	0	0	0
T24	15528	0	0	0
T27	593	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	433	0	0	0
T48	0	2	0	0
T107	772	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	369735085	149	0	0
CgEnOn_A	369735085	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735085	149	0	0
T18	2714	6	0	0
T19	2925	0	0	0
T20	2369	0	0	0
T21	3552	0	0	0
T22	11677	0	0	0
T23	18911	0	0	0
T24	112098	0	0	0
T27	2352	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	1670	0	0	0
T48	0	2	0	0
T107	2736	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T192	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735085	147	0	0
T18	2714	6	0	0
T19	2925	0	0	0
T20	2369	0	0	0
T21	3552	0	0	0
T22	11677	0	0	0
T23	18911	0	0	0
T24	112098	0	0	0
T27	2352	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	1670	0	0	0
T48	0	2	0	0
T107	2736	0	0	0
T185	0	1	0	0
T186	0	4	0	0
T187	0	4	0	0
T189	0	4	0	0
T190	0	4	0	0
T191	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396433898	145	0	0
CgEnOn_A	396433898	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	145	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T24	116774	0	0	0
T27	2450	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	1740	0	0	0
T48	0	1	0	0
T107	2850	0	0	0
T185	0	3	0	0
T186	0	4	0	0
T187	0	2	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	145	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T24	116774	0	0	0
T27	2450	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	1740	0	0	0
T48	0	1	0	0
T107	2850	0	0	0
T185	0	3	0	0
T186	0	4	0	0
T187	0	2	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396433898	145	0	0
CgEnOn_A	396433898	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	145	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T24	116774	0	0	0
T27	2450	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	1740	0	0	0
T48	0	1	0	0
T107	2850	0	0	0
T185	0	3	0	0
T186	0	4	0	0
T187	0	2	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	145	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T24	116774	0	0	0
T27	2450	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	1740	0	0	0
T48	0	1	0	0
T107	2850	0	0	0
T185	0	3	0	0
T186	0	4	0	0
T187	0	2	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	190472253	147	0	0
CgEnOn_A	190472253	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190472253	147	0	0
T18	1315	3	0	0
T19	1462	0	0	0
T20	1184	0	0	0
T21	1775	0	0	0
T22	5839	0	0	0
T23	9456	0	0	0
T24	56052	0	0	0
T27	1176	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	835	0	0	0
T71	0	1	0	0
T107	1368	0	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	5	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190472253	141	0	0
T18	1315	3	0	0
T19	1462	0	0	0
T20	1184	0	0	0
T21	1775	0	0	0
T22	5839	0	0	0
T23	9456	0	0	0
T24	56052	0	0	0
T27	1176	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	835	0	0	0
T71	0	1	0	0
T107	1368	0	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	5	0	0
T188	0	1	0	0
T189	0	5	0	0
T190	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	92043185	6862	0	0
CgEnOn_A	92043185	4589	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	6862	0	0
T1	36355	1	0	0
T2	133456	16	0	0
T3	190680	38	0	0
T4	2079	1	0	0
T5	1129	1	0	0
T6	1023	1	0	0
T17	1456	2	0	0
T18	665	7	0	0
T19	802	1	0	0
T20	576	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92043185	4589	0	0
T2	133456	12	0	0
T3	190680	27	0	0
T10	0	26	0	0
T11	0	63	0	0
T17	1456	1	0	0
T18	665	6	0	0
T19	802	0	0	0
T20	576	0	0	0
T21	964	0	0	0
T22	1566	0	0	0
T23	5088	0	0	0
T27	593	0	0	0
T75	0	10	0	0
T81	0	1	0	0
T104	0	9	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	184087578	6931	0	0
CgEnOn_A	184087578	4658	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184087578	6931	0	0
T1	72709	1	0	0
T2	266912	20	0	0
T3	381363	41	0	0
T4	4160	1	0	0
T5	2258	1	0	0
T6	2046	1	0	0
T17	2912	2	0	0
T18	1331	7	0	0
T19	1606	1	0	0
T20	1153	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184087578	4658	0	0
T2	266912	16	0	0
T3	381363	30	0	0
T10	0	28	0	0
T11	0	72	0	0
T17	2912	1	0	0
T18	1331	6	0	0
T19	1606	0	0	0
T20	1153	0	0	0
T21	1930	0	0	0
T22	3132	0	0	0
T23	10177	0	0	0
T27	1188	0	0	0
T75	0	11	0	0
T81	0	1	0	0
T104	0	9	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	369735085	6930	0	0
CgEnOn_A	369735085	4655	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735085	6930	0	0
T1	145484	1	0	0
T2	533577	19	0	0
T3	763377	42	0	0
T4	7090	1	0	0
T5	4333	1	0	0
T6	3729	1	0	0
T17	5944	2	0	0
T18	2714	7	0	0
T19	2925	1	0	0
T20	2369	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369735085	4655	0	0
T2	533577	15	0	0
T3	763377	31	0	0
T10	0	26	0	0
T11	0	67	0	0
T17	5944	1	0	0
T18	2714	6	0	0
T19	2925	0	0	0
T20	2369	0	0	0
T21	3552	0	0	0
T22	11677	0	0	0
T23	18911	0	0	0
T27	2352	0	0	0
T75	0	9	0	0
T81	0	1	0	0
T104	0	9	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	190472253	6940	0	0
CgEnOn_A	190472253	4663	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190472253	6940	0	0
T1	72745	1	0	0
T2	318642	19	0	0
T3	393227	41	0	0
T4	3545	1	0	0
T5	2166	1	0	0
T6	1865	1	0	0
T17	2972	2	0	0
T18	1315	4	0	0
T19	1462	1	0	0
T20	1184	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190472253	4663	0	0
T2	318642	15	0	0
T3	393227	30	0	0
T10	0	25	0	0
T11	0	64	0	0
T17	2972	1	0	0
T18	1315	3	0	0
T19	1462	0	0	0
T20	1184	0	0	0
T21	1775	0	0	0
T22	5839	0	0	0
T23	9456	0	0	0
T27	1176	0	0	0
T75	0	9	0	0
T81	0	1	0	0
T104	0	8	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396433898	3644	0	0
CgEnOn_A	396433898	3644	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3644	0	0
T2	627829	13	0	0
T3	807210	15	0	0
T10	0	26	0	0
T11	0	34	0	0
T12	0	14	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	2	0	0
T81	0	1	0	0
T118	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3644	0	0
T2	627829	13	0	0
T3	807210	15	0	0
T10	0	26	0	0
T11	0	34	0	0
T12	0	14	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	2	0	0
T81	0	1	0	0
T118	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396433898	3659	0	0
CgEnOn_A	396433898	3659	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3659	0	0
T2	627829	12	0	0
T3	807210	14	0	0
T10	0	19	0	0
T11	0	40	0	0
T12	0	17	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	5	0	0
T81	0	1	0	0
T118	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3659	0	0
T2	627829	12	0	0
T3	807210	14	0	0
T10	0	19	0	0
T11	0	40	0	0
T12	0	17	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	5	0	0
T81	0	1	0	0
T118	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396433898	3580	0	0
CgEnOn_A	396433898	3580	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3580	0	0
T2	627829	13	0	0
T3	807210	14	0	0
T10	0	28	0	0
T11	0	32	0	0
T12	0	14	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	5	0	0
T81	0	1	0	0
T118	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3580	0	0
T2	627829	13	0	0
T3	807210	14	0	0
T10	0	28	0	0
T11	0	32	0	0
T12	0	14	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	5	0	0
T81	0	1	0	0
T118	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T2,T3,T17
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396433898	3688	0	0
CgEnOn_A	396433898	3688	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3688	0	0
T2	627829	15	0	0
T3	807210	14	0	0
T10	0	29	0	0
T11	0	37	0	0
T12	0	16	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	6	0	0
T81	0	1	0	0
T118	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396433898	3688	0	0
T2	627829	15	0	0
T3	807210	14	0	0
T10	0	29	0	0
T11	0	37	0	0
T12	0	16	0	0
T17	6192	1	0	0
T18	2779	5	0	0
T19	3047	0	0	0
T20	2468	0	0	0
T21	3700	0	0	0
T22	12163	0	0	0
T23	19700	0	0	0
T27	2450	0	0	0
T76	0	6	0	0
T81	0	1	0	0
T118	0	1	0	0