Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	606083	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3513832

1

T4

5

T6

14

T1

243

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1013603	1			T4	8		T6	12		T1	51
values[0x0]	1427205	1			T4	1		T6	13		T1	258
values[0x1]	1679107	1			T4	5		T6	12		T1	268

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	333215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3786700

1

T4

8

T6

15

T1

337

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15200	1			T2	7		T18	1		T21	1
valid_sources[0x01]	15091	1			T2	11		T8	156		T22	2
valid_sources[0x02]	16315	1			T2	12		T8	122		T22	6
valid_sources[0x03]	16893	1			T2	11		T19	1		T21	3
valid_sources[0x04]	15999	1			T2	10		T8	169		T22	6
valid_sources[0x05]	16133	1			T2	9		T3	48		T19	1
valid_sources[0x06]	15227	1			T2	5		T8	129		T9	207
valid_sources[0x07]	16312	1			T2	9		T3	11		T20	1
valid_sources[0x08]	14961	1			T2	4		T19	1		T8	221
valid_sources[0x09]	16203	1			T2	10		T8	132		T22	7
valid_sources[0x0a]	17236	1			T2	14		T18	2		T8	182
valid_sources[0x0b]	16637	1			T2	8		T8	151		T22	2
valid_sources[0x0c]	16433	1			T2	11		T8	167		T9	218
valid_sources[0x0d]	15760	1			T2	12		T8	124		T22	3
valid_sources[0x0e]	16753	1			T1	577		T2	6		T8	78
valid_sources[0x0f]	16425	1			T2	7		T18	2		T21	5
valid_sources[0x10]	15067	1			T2	9		T21	2		T8	119
valid_sources[0x11]	15405	1			T2	9		T8	122		T22	9
valid_sources[0x12]	17172	1			T2	6		T19	2		T20	1
valid_sources[0x13]	15989	1			T2	14		T8	200		T22	7
valid_sources[0x14]	16892	1			T2	4		T18	2		T21	1
valid_sources[0x15]	17207	1			T2	7		T18	1		T8	110
valid_sources[0x16]	17281	1			T2	14		T8	70		T22	3
valid_sources[0x17]	15579	1			T2	6		T18	2		T21	1
valid_sources[0x18]	15842	1			T4	1		T2	14		T18	1
valid_sources[0x19]	16291	1			T2	12		T19	2		T8	108
valid_sources[0x1a]	17507	1			T2	8		T8	75		T22	2
valid_sources[0x1b]	16155	1			T2	5		T21	1		T8	118
valid_sources[0x1c]	16980	1			T2	10		T8	65		T22	1
valid_sources[0x1d]	16809	1			T2	9		T3	54		T8	109
valid_sources[0x1e]	17392	1			T2	10		T3	75		T21	1
valid_sources[0x1f]	16394	1			T2	8		T18	1		T8	144
valid_sources[0x20]	16838	1			T2	10		T18	1		T19	1
valid_sources[0x21]	16200	1			T2	12		T8	145		T22	7
valid_sources[0x22]	17143	1			T2	13		T3	25		T18	1
valid_sources[0x23]	14869	1			T2	11		T21	2		T8	125
valid_sources[0x24]	16816	1			T2	10		T18	1		T8	181
valid_sources[0x25]	15645	1			T2	4		T19	2		T8	155
valid_sources[0x26]	16479	1			T2	7		T8	99		T31	4
valid_sources[0x27]	14943	1			T2	12		T8	157		T22	8
valid_sources[0x28]	15205	1			T2	11		T8	205		T22	5
valid_sources[0x29]	15488	1			T2	6		T19	1		T8	183
valid_sources[0x2a]	15954	1			T2	5		T18	1		T8	196
valid_sources[0x2b]	17543	1			T2	9		T19	3		T8	191
valid_sources[0x2c]	14527	1			T2	11		T18	2		T8	197
valid_sources[0x2d]	15383	1			T2	6		T8	139		T9	216
valid_sources[0x2e]	16127	1			T4	1		T2	9		T8	168
valid_sources[0x2f]	15288	1			T2	7		T18	1		T20	1
valid_sources[0x30]	16529	1			T2	10		T8	173		T9	181
valid_sources[0x31]	16724	1			T2	7		T8	111		T9	210
valid_sources[0x32]	15889	1			T2	9		T8	68		T22	5
valid_sources[0x33]	16754	1			T2	12		T18	1		T21	1
valid_sources[0x34]	16504	1			T2	5		T3	9		T18	2
valid_sources[0x35]	16315	1			T2	13		T18	3		T19	2
valid_sources[0x36]	17940	1			T2	7		T8	199		T9	199
valid_sources[0x37]	15336	1			T2	10		T20	3		T21	1
valid_sources[0x38]	15891	1			T2	13		T8	107		T22	1
valid_sources[0x39]	17893	1			T2	6		T8	208		T22	1
valid_sources[0x3a]	16505	1			T2	9		T8	80		T9	220
valid_sources[0x3b]	15821	1			T2	13		T19	1		T8	115
valid_sources[0x3c]	16552	1			T2	4		T21	1		T8	86
valid_sources[0x3d]	15112	1			T2	11		T21	1		T8	70
valid_sources[0x3e]	15358	1			T2	9		T8	190		T72	31
valid_sources[0x3f]	16232	1			T2	8		T19	3		T8	130
valid_sources[0x40]	15402	1			T2	8		T8	76		T22	1
valid_sources[0x41]	15774	1			T4	2		T2	8		T8	87
valid_sources[0x42]	16413	1			T2	5		T3	92		T18	1
valid_sources[0x43]	14847	1			T2	12		T18	1		T19	1
valid_sources[0x44]	15398	1			T2	6		T8	261		T22	4
valid_sources[0x45]	16896	1			T2	6		T21	1		T8	208
valid_sources[0x46]	14639	1			T2	6		T8	76		T22	8
valid_sources[0x47]	15291	1			T2	4		T3	27		T18	1
valid_sources[0x48]	15994	1			T2	15		T3	66		T8	74
valid_sources[0x49]	15945	1			T2	15		T19	2		T8	116
valid_sources[0x4a]	15243	1			T2	12		T8	172		T22	2
valid_sources[0x4b]	16171	1			T2	9		T8	141		T22	1
valid_sources[0x4c]	15634	1			T2	9		T8	141		T22	2
valid_sources[0x4d]	15481	1			T2	12		T8	105		T22	7
valid_sources[0x4e]	15739	1			T2	10		T3	53		T8	124
valid_sources[0x4f]	15943	1			T2	5		T3	59		T20	1
valid_sources[0x50]	15664	1			T2	11		T8	270		T22	1
valid_sources[0x51]	15741	1			T2	3		T8	198		T22	2
valid_sources[0x52]	16684	1			T2	12		T18	1		T20	2
valid_sources[0x53]	16615	1			T2	15		T21	4		T8	179
valid_sources[0x54]	17502	1			T2	9		T8	122		T22	1
valid_sources[0x55]	16617	1			T2	11		T19	1		T21	1
valid_sources[0x56]	15552	1			T2	6		T3	53		T8	81
valid_sources[0x57]	16579	1			T2	11		T18	1		T8	155
valid_sources[0x58]	15341	1			T2	19		T8	105		T22	1
valid_sources[0x59]	16127	1			T2	10		T18	2		T8	78
valid_sources[0x5a]	15709	1			T2	7		T18	2		T21	2
valid_sources[0x5b]	16499	1			T2	8		T18	1		T8	117
valid_sources[0x5c]	15456	1			T2	7		T19	1		T20	1
valid_sources[0x5d]	15956	1			T2	12		T21	1		T8	115
valid_sources[0x5e]	16462	1			T2	6		T8	162		T22	1
valid_sources[0x5f]	16180	1			T4	2		T2	13		T8	115
valid_sources[0x60]	16060	1			T2	7		T8	55		T9	229
valid_sources[0x61]	15932	1			T2	11		T8	133		T9	186
valid_sources[0x62]	14936	1			T2	10		T19	2		T8	109
valid_sources[0x63]	16998	1			T2	9		T8	113		T9	231
valid_sources[0x64]	17260	1			T2	9		T18	2		T19	1
valid_sources[0x65]	16323	1			T2	10		T19	1		T8	188
valid_sources[0x66]	16055	1			T2	9		T20	1		T8	138
valid_sources[0x67]	16734	1			T2	11		T18	1		T8	101
valid_sources[0x68]	17610	1			T2	9		T8	151		T9	169
valid_sources[0x69]	16802	1			T2	8		T8	59		T22	1
valid_sources[0x6a]	15997	1			T2	18		T19	1		T8	178
valid_sources[0x6b]	15734	1			T2	12		T8	171		T22	5
valid_sources[0x6c]	15925	1			T2	11		T18	3		T21	1
valid_sources[0x6d]	16123	1			T2	6		T3	4		T8	177
valid_sources[0x6e]	15243	1			T2	12		T8	99		T22	1
valid_sources[0x6f]	15942	1			T2	7		T8	132		T22	2
valid_sources[0x70]	15852	1			T2	11		T8	128		T22	7
valid_sources[0x71]	15864	1			T2	8		T8	47		T22	2
valid_sources[0x72]	15244	1			T2	13		T21	1		T8	107
valid_sources[0x73]	15073	1			T2	5		T18	1		T8	277
valid_sources[0x74]	15030	1			T2	5		T21	1		T8	67
valid_sources[0x75]	16064	1			T2	9		T21	1		T8	137
valid_sources[0x76]	17089	1			T2	12		T20	1		T8	139
valid_sources[0x77]	15798	1			T2	17		T8	129		T31	5
valid_sources[0x78]	15791	1			T2	10		T18	1		T8	71
valid_sources[0x79]	15709	1			T2	6		T18	1		T19	1
valid_sources[0x7a]	15410	1			T2	12		T3	41		T19	1
valid_sources[0x7b]	14810	1			T2	14		T18	1		T8	64
valid_sources[0x7c]	16280	1			T2	9		T8	130		T22	9
valid_sources[0x7d]	15522	1			T2	14		T8	194		T9	199
valid_sources[0x7e]	15583	1			T2	6		T3	27		T8	103
valid_sources[0x7f]	17427	1			T2	10		T3	7		T8	318
valid_sources[0x80]	14174	1			T2	15		T19	1		T20	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

887276

1

T4

4

T6

6

T1

28

values[0x0]

all_enables

biggest_size

1336152

1

T4

1

T6

4

T1

154

values[0x1]

all_enables

biggest_size

1290404

1

T6

4

T1

61

T2

355