Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	813789275	72475	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813789275	72475	0	0
T1	938760	95	0	0
T2	549460	488	0	0
T3	852770	335	0	0
T8	0	730	0	0
T9	0	392	0	0
T10	0	177	0	0
T11	0	174	0	0
T12	0	745	0	0
T13	0	282	0	0
T14	0	1394	0	0
T15	4465	0	0	0
T16	10065	0	0	0
T17	7125	0	0	0
T18	8650	0	0	0
T19	8560	0	0	0
T20	5835	0	0	0
T21	7840	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162757855	10655	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	10655	0	0
T1	187752	13	0	0
T2	109892	63	0	0
T3	170554	49	0	0
T8	0	119	0	0
T9	0	57	0	0
T10	0	27	0	0
T11	0	27	0	0
T12	0	114	0	0
T13	0	38	0	0
T14	0	221	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T21	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162757855	10526	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	10526	0	0
T1	187752	13	0	0
T2	109892	70	0	0
T3	170554	48	0	0
T8	0	114	0	0
T9	0	57	0	0
T10	0	27	0	0
T11	0	27	0	0
T12	0	113	0	0
T13	0	37	0	0
T14	0	219	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T21	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162757855	14564	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	14564	0	0
T1	187752	19	0	0
T2	109892	97	0	0
T3	170554	67	0	0
T8	0	147	0	0
T9	0	78	0	0
T10	0	36	0	0
T11	0	35	0	0
T12	0	150	0	0
T13	0	57	0	0
T14	0	281	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T21	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162757855	14579	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	14579	0	0
T1	187752	20	0	0
T2	109892	96	0	0
T3	170554	67	0	0
T8	0	147	0	0
T9	0	78	0	0
T10	0	36	0	0
T11	0	36	0	0
T12	0	149	0	0
T13	0	58	0	0
T14	0	278	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T21	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	162757855	22151	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	22151	0	0
T1	187752	30	0	0
T2	109892	162	0	0
T3	170554	104	0	0
T8	0	203	0	0
T9	0	122	0	0
T10	0	51	0	0
T11	0	49	0	0
T12	0	219	0	0
T13	0	92	0	0
T14	0	395	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T21	1568	0	0	0