Module Definition
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Module : prim_generic_clock_div
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_no_scan_io_div2_div


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_div2.u_div2 100.00 100.00 100.00
gen_div2.u_inv 100.00 100.00
gen_div2.u_step_down_mux 100.00 100.00 100.00 100.00
u_clk_div_buf 100.00 100.00
u_clk_mux 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_no_scan_io_div4_div


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_clk_div_buf 100.00 100.00
u_clk_mux 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2711100.00
ALWAYS5533100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
27 1 1
55 1 1
56 1 1
58 1 1
72 1 1

Line Coverage for Module : prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN8111100.00
ALWAYS8577100.00
ALWAYS9733100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
27 1 1
81 1 1
85 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1
92 1 1
97 1 1
98 1 1
100 1 1

Cond Coverage for Module : prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T1,T15
Cond Coverage for Module : prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T1,T15 

 LINE       81
 EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
             ---------1--------
-1-StatusTests
0CoveredT6,T1,T15
1CoveredT4,T5,T6
Branch Coverage for Module : prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 27 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	27	(test_en_i) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T15
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Branch Coverage for Module : prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 27 2 2 100.00
TERNARY 81 2 2 100.00
IF 85 3 3 100.00
IF 97 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	27	(test_en_i) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T15
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	81	((!step_down_req)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T6,T1,T15 



	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	88	if ((gen_div.cnt >= gen_div.limit))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	97	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Module : prim_generic_clock_div
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DivEven_A 1610 1610 0 0


DivEven_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1610 1610 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2711100.00
ALWAYS5533100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
27 1 1
55 1 1
56 1 1
58 1 1
72 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T1,T15
Branch Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 27 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	27	(test_en_i) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T15
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DivEven_A 805 805 0 0


DivEven_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN8111100.00
ALWAYS8577100.00
ALWAYS9733100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
27 1 1
81 1 1
85 1 1
86 1 1
87 1 1
88 1 1
89 1 1
90 1 1
92 1 1
97 1 1
98 1 1
100 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       27
 EXPRESSION (test_en_i ? '0 : step_down_req_i)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T1,T15 

 LINE       81
 EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
             ---------1--------
-1-StatusTests
0CoveredT6,T1,T15
1CoveredT4,T5,T6
Branch Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 27 2 2 100.00
TERNARY 81 2 2 100.00
IF 85 3 3 100.00
IF 97 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv' or '../src/lowrisc_prim_generic_clock_div_0/rtl/prim_generic_clock_div.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	27	(test_en_i) ?

Branches:
-1-StatusTests
1 Covered T4,T1,T15
0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	81	((!step_down_req)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T6,T1,T15 



	LineNo.	Expression
-1-:	85	if ((!rst_ni))
-2-:	88	if ((gen_div.cnt >= gen_div.limit))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T4,T5,T6
0 0 Covered T4,T5,T6 



	LineNo.	Expression
-1-:	97	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DivEven_A 805 805 0 0


DivEven_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 805 805 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%