Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	162757855	160516255	0	0
AllClkBypReqTrue_A	162757855	135418	0	0
IoClkBypReqFalse_A	162757855	160433078	0	2415
IoClkBypReqTrue_A	162757855	213813	0	0
LcClkBypAckFalse_A	162757855	160524750	0	0
LcClkBypAckTrue_A	162757855	126923	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	160516255	0	0
T1	187752	187131	0	0
T2	109892	109724	0	0
T3	170554	169783	0	0
T4	1229	1147	0	0
T5	1083	1051	0	0
T6	2179	1757	0	0
T15	893	802	0	0
T16	2013	1891	0	0
T17	1425	1321	0	0
T18	1730	1561	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	135418	0	0
T1	187752	142	0	0
T2	109892	215	0	0
T3	170554	71	0	0
T6	2179	259	0	0
T8	0	1233	0	0
T9	0	2008	0	0
T15	893	40	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T72	0	204	0	0
T117	0	294	0	0
T118	0	107	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	160433078	0	2415
T1	187752	186886	0	3
T2	109892	109687	0	3
T3	170554	169589	0	3
T4	1229	1145	0	3
T5	1083	1049	0	3
T6	2179	1649	0	3
T15	893	736	0	3
T16	2013	1889	0	3
T17	1425	1319	0	3
T18	1730	1559	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	213813	0	0
T1	187752	381	0	0
T2	109892	574	0	0
T3	170554	249	0	0
T6	2179	365	0	0
T8	0	1667	0	0
T9	0	2439	0	0
T15	893	104	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T72	0	382	0	0
T117	0	357	0	0
T119	0	317	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	160524750	0	0
T1	187752	187058	0	0
T2	109892	109707	0	0
T3	170554	169776	0	0
T4	1229	1147	0	0
T5	1083	1051	0	0
T6	2179	1742	0	0
T15	893	813	0	0
T16	2013	1891	0	0
T17	1425	1321	0	0
T18	1730	1561	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	126923	0	0
T1	187752	215	0	0
T2	109892	386	0	0
T3	170554	78	0	0
T6	2179	274	0	0
T8	0	1116	0	0
T9	0	1723	0	0
T15	893	29	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T72	0	157	0	0
T117	0	178	0	0
T119	0	75	0	0