Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2141094720	15670	0	0
TransStop_A	2141094720	8144	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141094720	15670	0	0
T1	732675	0	0	0
T2	415568	13	0	0
T3	1392264	49	0	0
T4	3798	3	0	0
T5	11868	0	0	0
T6	6813	0	0	0
T8	599020	55	0	0
T9	0	27	0	0
T15	11181	0	0	0
T16	8392	0	0	0
T17	8936	0	0	0
T18	6924	4	0	0
T19	3425	26	0	0
T20	4674	8	0	0
T21	3138	15	0	0
T22	110750	0	0	0
T31	0	39	0	0
T73	0	17	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2141094720	8144	0	0
T1	244225	0	0	0
T2	415568	13	0	0
T3	1392264	19	0	0
T4	1266	1	0	0
T5	3956	0	0	0
T6	2271	0	0	0
T8	1797060	31	0	0
T9	0	51	0	0
T11	0	2	0	0
T15	3727	0	0	0
T16	8392	0	0	0
T17	8936	0	0	0
T18	6924	4	0	0
T19	10275	12	0	0
T20	14022	3	0	0
T21	9414	11	0	0
T22	332250	0	0	0
T31	0	26	0	0
T73	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	535273680	3966	0	0
TransStop_A	535273680	2075	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	3966	0	0
T1	244225	0	0	0
T2	103892	3	0	0
T3	348066	14	0	0
T4	1266	1	0	0
T5	3956	0	0	0
T6	2271	0	0	0
T8	0	11	0	0
T15	3727	0	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T21	0	3	0	0
T31	0	7	0	0
T73	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	2075	0	0
T2	103892	3	0	0
T3	348066	6	0	0
T8	599020	5	0	0
T9	0	20	0	0
T11	0	1	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	3425	3	0	0
T20	4674	0	0	0
T21	3138	1	0	0
T22	110750	0	0	0
T31	0	6	0	0
T73	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	535273680	3857	0	0
TransStop_A	535273680	2025	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	3857	0	0
T1	244225	0	0	0
T2	103892	3	0	0
T3	348066	14	0	0
T4	1266	1	0	0
T5	3956	0	0	0
T6	2271	0	0	0
T8	0	16	0	0
T15	3727	0	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	0	6	0	0
T20	0	4	0	0
T21	0	3	0	0
T31	0	14	0	0
T73	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	2025	0	0
T1	244225	0	0	0
T2	103892	3	0	0
T3	348066	5	0	0
T4	1266	1	0	0
T5	3956	0	0	0
T6	2271	0	0	0
T8	0	10	0	0
T15	3727	0	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	0	2	0	0
T20	0	2	0	0
T21	0	3	0	0
T31	0	9	0	0
T73	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	535273680	3925	0	0
TransStop_A	535273680	2031	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	3925	0	0
T2	103892	3	0	0
T3	348066	9	0	0
T8	599020	14	0	0
T9	0	27	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	3425	7	0	0
T20	4674	1	0	0
T21	3138	4	0	0
T22	110750	0	0	0
T31	0	9	0	0
T73	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	2031	0	0
T2	103892	3	0	0
T3	348066	4	0	0
T8	599020	8	0	0
T9	0	14	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	3425	3	0	0
T20	4674	1	0	0
T21	3138	2	0	0
T22	110750	0	0	0
T31	0	7	0	0
T73	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	535273680	3922	0	0
TransStop_A	535273680	2013	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	3922	0	0
T1	244225	0	0	0
T2	103892	4	0	0
T3	348066	12	0	0
T4	1266	1	0	0
T5	3956	0	0	0
T6	2271	0	0	0
T8	0	14	0	0
T15	3727	0	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	0	9	0	0
T20	0	1	0	0
T21	0	5	0	0
T31	0	9	0	0
T73	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273680	2013	0	0
T2	103892	4	0	0
T3	348066	4	0	0
T8	599020	8	0	0
T9	0	17	0	0
T11	0	1	0	0
T16	2098	0	0	0
T17	2234	0	0	0
T18	1731	1	0	0
T19	3425	4	0	0
T20	4674	0	0	0
T21	3138	5	0	0
T22	110750	0	0	0
T31	0	4	0	0
T73	0	3	0	0