Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	163714608	5143993	0	0
clk_enables_rd_A	163714608	49828	0	0
clk_hints_rd_A	163714608	45250	0	0
extclk_ctrl_rd_A	163714608	56350	0	0
extclk_ctrl_regwen_rd_A	163714608	42907	0	0
jitter_enable_rd_A	163714608	63858	0	0
jitter_regwen_rd_A	163714608	47290	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163714608	5143993	0	0
T8	150355	45752	0	0
T9	199967	69165	0	0
T10	63171	0	0	0
T14	0	149288	0	0
T22	106316	0	0	0
T23	54132	0	0	0
T24	0	74519	0	0
T27	871	0	0	0
T30	1472	0	0	0
T31	3213	0	0	0
T66	0	83488	0	0
T67	0	89106	0	0
T68	0	89390	0	0
T69	0	167093	0	0
T70	0	95292	0	0
T71	0	68555	0	0
T72	2206	0	0	0
T73	1884	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163714608	49828	0	0
T8	150355	866	0	0
T9	199967	0	0	0
T10	63171	0	0	0
T12	0	2	0	0
T22	106316	0	0	0
T23	54132	0	0	0
T24	0	2770	0	0
T27	871	0	0	0
T28	0	17	0	0
T30	1472	0	0	0
T31	3213	0	0	0
T67	0	3507	0	0
T72	2206	0	0	0
T73	1884	0	0	0
T87	0	2	0	0
T94	0	1262	0	0
T95	0	6037	0	0
T141	0	22	0	0
T142	0	3720	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163714608	45250	0	0
T3	170554	3	0	0
T8	150355	968	0	0
T12	0	5	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T21	1568	0	0	0
T22	106316	0	0	0
T24	0	2473	0	0
T28	0	8	0	0
T30	1472	0	0	0
T67	0	3073	0	0
T72	2206	0	0	0
T87	0	2	0	0
T94	0	1300	0	0
T141	0	5	0	0
T142	0	3147	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163714608	56350	0	0
T1	187752	0	0	0
T2	109892	0	0	0
T3	170554	17	0	0
T6	2179	53	0	0
T8	0	1068	0	0
T12	0	96	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T24	0	2933	0	0
T105	0	14	0	0
T118	0	48	0	0
T143	0	76	0	0
T144	0	13	0	0
T145	0	10	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163714608	42907	0	0
T8	150355	885	0	0
T9	199967	0	0	0
T10	63171	0	0	0
T22	106316	0	0	0
T23	54132	0	0	0
T24	0	2263	0	0
T27	871	0	0	0
T30	1472	0	0	0
T31	3213	0	0	0
T67	0	2910	0	0
T72	2206	0	0	0
T73	1884	0	0	0
T94	0	1077	0	0
T95	0	5556	0	0
T105	0	3	0	0
T106	0	63	0	0
T142	0	3082	0	0
T146	0	63	0	0
T147	0	34	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163714608	63858	0	0
T3	170554	162	0	0
T8	150355	1086	0	0
T12	0	154	0	0
T17	1425	0	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T20	1167	0	0	0
T21	1568	0	0	0
T22	106316	0	0	0
T24	0	3219	0	0
T28	0	229	0	0
T30	1472	0	0	0
T67	0	5321	0	0
T72	2206	0	0	0
T87	0	92	0	0
T94	0	1463	0	0
T141	0	343	0	0
T142	0	4575	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163714608	47290	0	0
T8	150355	1054	0	0
T9	199967	0	0	0
T10	63171	0	0	0
T22	106316	0	0	0
T23	54132	0	0	0
T24	0	2635	0	0
T27	871	0	0	0
T30	1472	0	0	0
T31	3213	0	0	0
T67	0	3655	0	0
T72	2206	0	0	0
T73	1884	0	0	0
T94	0	1104	0	0
T95	0	6088	0	0
T142	0	3637	0	0
T148	0	1004	0	0
T149	0	3749	0	0
T150	0	2367	0	0
T151	0	6635	0	0