Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	488273565	453	0	0
StatusRise_A	488273565	453	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488273565	453	0	0
T1	563256	0	0	0
T2	329676	0	0	0
T3	511662	0	0	0
T5	3249	11	0	0
T6	6537	0	0	0
T15	2679	0	0	0
T16	6039	0	0	0
T17	4275	14	0	0
T18	5190	0	0	0
T19	5136	0	0	0
T30	0	4	0	0
T152	0	3	0	0
T153	0	15	0	0
T154	0	9	0	0
T155	0	13	0	0
T156	0	17	0	0
T157	0	12	0	0
T158	0	9	0	0
T159	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488273565	453	0	0
T1	563256	0	0	0
T2	329676	0	0	0
T3	511662	0	0	0
T5	3249	11	0	0
T6	6537	0	0	0
T15	2679	0	0	0
T16	6039	0	0	0
T17	4275	14	0	0
T18	5190	0	0	0
T19	5136	0	0	0
T30	0	4	0	0
T152	0	3	0	0
T153	0	15	0	0
T154	0	9	0	0
T155	0	13	0	0
T156	0	17	0	0
T157	0	12	0	0
T158	0	9	0	0
T159	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	162757855	143	0	0
StatusRise_A	162757855	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	143	0	0
T1	187752	0	0	0
T2	109892	0	0	0
T3	170554	0	0	0
T5	1083	4	0	0
T6	2179	0	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	5	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T30	0	1	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	143	0	0
T1	187752	0	0	0
T2	109892	0	0	0
T3	170554	0	0	0
T5	1083	4	0	0
T6	2179	0	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	5	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T30	0	1	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	162757855	153	0	0
StatusRise_A	162757855	153	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	153	0	0
T1	187752	0	0	0
T2	109892	0	0	0
T3	170554	0	0	0
T5	1083	4	0	0
T6	2179	0	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	4	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T30	0	2	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0
T158	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	153	0	0
T1	187752	0	0	0
T2	109892	0	0	0
T3	170554	0	0	0
T5	1083	4	0	0
T6	2179	0	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	4	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T30	0	2	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0
T158	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	162757855	157	0	0
StatusRise_A	162757855	157	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	157	0	0
T1	187752	0	0	0
T2	109892	0	0	0
T3	170554	0	0	0
T5	1083	3	0	0
T6	2179	0	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	5	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T30	0	1	0	0
T152	0	1	0	0
T153	0	6	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	8	0	0
T157	0	3	0	0
T158	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162757855	157	0	0
T1	187752	0	0	0
T2	109892	0	0	0
T3	170554	0	0	0
T5	1083	3	0	0
T6	2179	0	0	0
T15	893	0	0	0
T16	2013	0	0	0
T17	1425	5	0	0
T18	1730	0	0	0
T19	1712	0	0	0
T30	0	1	0	0
T152	0	1	0	0
T153	0	6	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	8	0	0
T157	0	3	0	0
T158	0	3	0	0