Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49284	0	0
CgEnOn_A	2147483647	39711	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49284	0	0
T1	2579980	37	0	0
T2	5219242	94	0	0
T3	3758122	198	0	0
T4	6503	4	0	0
T5	42838	39	0	0
T6	25002	3	0	0
T15	40414	3	0	0
T16	22468	3	0	0
T17	24146	40	0	0
T18	18636	7	0	0
T19	19267	4	0	0
T20	0	2	0	0
T21	0	3	0	0
T30	0	10	0	0
T69	0	5	0	0
T152	0	10	0	0
T153	0	20	0	0
T154	0	10	0	0
T155	0	25	0	0
T156	0	25	0	0
T157	0	30	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39711	0	0
T1	2579980	28	0	0
T2	5219242	67	0	0
T3	3758122	174	0	0
T4	3798	1	0	0
T5	42838	36	0	0
T6	25002	0	0	0
T8	0	179	0	0
T9	0	311	0	0
T15	40414	0	0	0
T16	22468	0	0	0
T17	24146	37	0	0
T18	18636	4	0	0
T19	26635	4	0	0
T20	0	2	0	0
T30	0	16	0	0
T69	0	4	0	0
T152	0	10	0	0
T153	0	20	0	0
T154	0	10	0	0
T155	0	25	0	0
T156	0	25	0	0
T157	0	30	0	0
T158	0	3	0	0
T160	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	251414372	157	0	0
CgEnOn_A	251414372	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251414372	157	0	0
T1	108581	0	0	0
T2	449920	0	0	0
T3	166829	0	0	0
T5	1883	4	0	0
T6	1213	0	0	0
T15	1832	0	0	0
T16	960	0	0	0
T17	1044	4	0	0
T18	818	0	0	0
T19	1625	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251414372	157	0	0
T1	108581	0	0	0
T2	449920	0	0	0
T3	166829	0	0	0
T5	1883	4	0	0
T6	1213	0	0	0
T15	1832	0	0	0
T16	960	0	0	0
T17	1044	4	0	0
T18	818	0	0	0
T19	1625	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	125706541	157	0	0
CgEnOn_A	125706541	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	157	0	0
T1	54290	0	0	0
T2	224958	0	0	0
T3	83414	0	0	0
T5	941	4	0	0
T6	605	0	0	0
T15	916	0	0	0
T16	480	0	0	0
T17	522	4	0	0
T18	409	0	0	0
T19	812	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	157	0	0
T1	54290	0	0	0
T2	224958	0	0	0
T3	83414	0	0	0
T5	941	4	0	0
T6	605	0	0	0
T15	916	0	0	0
T16	480	0	0	0
T17	522	4	0	0
T18	409	0	0	0
T19	812	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	125706541	157	0	0
CgEnOn_A	125706541	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	157	0	0
T1	54290	0	0	0
T2	224958	0	0	0
T3	83414	0	0	0
T5	941	4	0	0
T6	605	0	0	0
T15	916	0	0	0
T16	480	0	0	0
T17	522	4	0	0
T18	409	0	0	0
T19	812	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	157	0	0
T1	54290	0	0	0
T2	224958	0	0	0
T3	83414	0	0	0
T5	941	4	0	0
T6	605	0	0	0
T15	916	0	0	0
T16	480	0	0	0
T17	522	4	0	0
T18	409	0	0	0
T19	812	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	125706541	157	0	0
CgEnOn_A	125706541	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	157	0	0
T1	54290	0	0	0
T2	224958	0	0	0
T3	83414	0	0	0
T5	941	4	0	0
T6	605	0	0	0
T15	916	0	0	0
T16	480	0	0	0
T17	522	4	0	0
T18	409	0	0	0
T19	812	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	157	0	0
T1	54290	0	0	0
T2	224958	0	0	0
T3	83414	0	0	0
T5	941	4	0	0
T6	605	0	0	0
T15	916	0	0	0
T16	480	0	0	0
T17	522	4	0	0
T18	409	0	0	0
T19	812	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504213697	157	0	0
CgEnOn_A	504213697	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504213697	157	0	0
T1	217168	0	0	0
T2	899418	0	0	0
T3	334132	0	0	0
T5	3831	4	0	0
T6	2179	0	0	0
T15	3577	0	0	0
T16	2013	0	0	0
T17	2181	4	0	0
T18	1661	0	0	0
T19	3288	0	0	0
T30	0	2	0	0
T69	0	1	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504213697	156	0	0
T1	217168	0	0	0
T2	899418	0	0	0
T3	334132	0	0	0
T5	3831	4	0	0
T6	2179	0	0	0
T15	3577	0	0	0
T16	2013	0	0	0
T17	2181	4	0	0
T18	1661	0	0	0
T19	3288	0	0	0
T30	0	2	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	5	0	0
T156	0	5	0	0
T157	0	6	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	535273251	147	0	0
CgEnOn_A	535273251	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	147	0	0
T1	244224	0	0	0
T2	103892	0	0	0
T3	348066	0	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T9	0	1	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	0	0	0
T19	3425	0	0	0
T30	0	1	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	3	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	144	0	0
T1	244224	0	0	0
T2	103892	0	0	0
T3	348066	0	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T9	0	1	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	0	0	0
T19	3425	0	0	0
T30	0	1	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	3	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	535273251	147	0	0
CgEnOn_A	535273251	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	147	0	0
T1	244224	0	0	0
T2	103892	0	0	0
T3	348066	0	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T9	0	1	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	0	0	0
T19	3425	0	0	0
T30	0	1	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	3	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	144	0	0
T1	244224	0	0	0
T2	103892	0	0	0
T3	348066	0	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T9	0	1	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	0	0	0
T19	3425	0	0	0
T30	0	1	0	0
T153	0	5	0	0
T154	0	4	0	0
T155	0	5	0	0
T156	0	4	0	0
T157	0	3	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	257068574	160	0	0
CgEnOn_A	257068574	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257068574	160	0	0
T1	122989	0	0	0
T2	498691	0	0	0
T3	167074	0	0	0
T5	1955	3	0	0
T6	1089	0	0	0
T15	1788	0	0	0
T16	1007	0	0	0
T17	1105	5	0	0
T18	831	0	0	0
T19	1643	0	0	0
T30	0	1	0	0
T152	0	1	0	0
T153	0	6	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	8	0	0
T157	0	3	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257068574	158	0	0
T1	122989	0	0	0
T2	498691	0	0	0
T3	167074	0	0	0
T5	1955	3	0	0
T6	1089	0	0	0
T15	1788	0	0	0
T16	1007	0	0	0
T17	1105	5	0	0
T18	831	0	0	0
T19	1643	0	0	0
T30	0	1	0	0
T152	0	1	0	0
T153	0	6	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	8	0	0
T157	0	3	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	125706541	7935	0	0
CgEnOn_A	125706541	5548	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	7935	0	0
T1	54290	12	0	0
T2	224958	30	0	0
T3	83414	60	0	0
T4	294	1	0	0
T5	941	5	0	0
T6	605	1	0	0
T15	916	1	0	0
T16	480	1	0	0
T17	522	5	0	0
T18	409	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125706541	5548	0	0
T1	54290	9	0	0
T2	224958	21	0	0
T3	83414	52	0	0
T5	941	4	0	0
T6	605	0	0	0
T8	0	56	0	0
T9	0	104	0	0
T15	916	0	0	0
T16	480	0	0	0
T17	522	4	0	0
T18	409	1	0	0
T19	812	0	0	0
T30	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	251414372	7934	0	0
CgEnOn_A	251414372	5547	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251414372	7934	0	0
T1	108581	13	0	0
T2	449920	32	0	0
T3	166829	62	0	0
T4	588	1	0	0
T5	1883	5	0	0
T6	1213	1	0	0
T15	1832	1	0	0
T16	960	1	0	0
T17	1044	5	0	0
T18	818	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251414372	5547	0	0
T1	108581	10	0	0
T2	449920	23	0	0
T3	166829	54	0	0
T5	1883	4	0	0
T6	1213	0	0	0
T8	0	54	0	0
T9	0	104	0	0
T15	1832	0	0	0
T16	960	0	0	0
T17	1044	4	0	0
T18	818	1	0	0
T19	1625	0	0	0
T30	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	504213697	7963	0	0
CgEnOn_A	504213697	5575	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504213697	7963	0	0
T1	217168	12	0	0
T2	899418	29	0	0
T3	334132	62	0	0
T4	1215	1	0	0
T5	3831	5	0	0
T6	2179	1	0	0
T15	3577	1	0	0
T16	2013	1	0	0
T17	2181	5	0	0
T18	1661	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504213697	5575	0	0
T1	217168	9	0	0
T2	899418	20	0	0
T3	334132	54	0	0
T5	3831	4	0	0
T6	2179	0	0	0
T8	0	58	0	0
T9	0	103	0	0
T15	3577	0	0	0
T16	2013	0	0	0
T17	2181	4	0	0
T18	1661	1	0	0
T19	3288	0	0	0
T30	0	2	0	0
T160	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T17,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	257068574	7955	0	0
CgEnOn_A	257068574	5565	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257068574	7955	0	0
T1	122989	13	0	0
T2	498691	32	0	0
T3	167074	62	0	0
T4	608	1	0	0
T5	1955	4	0	0
T6	1089	1	0	0
T15	1788	1	0	0
T16	1007	1	0	0
T17	1105	6	0	0
T18	831	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	257068574	5565	0	0
T1	122989	10	0	0
T2	498691	23	0	0
T3	167074	54	0	0
T5	1955	3	0	0
T6	1089	0	0	0
T8	0	56	0	0
T9	0	103	0	0
T15	1788	0	0	0
T16	1007	0	0	0
T17	1105	5	0	0
T18	831	1	0	0
T19	1643	0	0	0
T30	0	1	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	535273251	4113	0	0
CgEnOn_A	535273251	4110	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4113	0	0
T1	244224	0	0	0
T2	103892	3	0	0
T3	348066	14	0	0
T4	1266	1	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	11	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T21	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4110	0	0
T1	244224	0	0	0
T2	103892	3	0	0
T3	348066	14	0	0
T4	1266	1	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	11	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T21	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	535273251	4004	0	0
CgEnOn_A	535273251	4001	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4004	0	0
T1	244224	0	0	0
T2	103892	3	0	0
T3	348066	14	0	0
T4	1266	1	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	16	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	0	6	0	0
T20	0	4	0	0
T21	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4001	0	0
T1	244224	0	0	0
T2	103892	3	0	0
T3	348066	14	0	0
T4	1266	1	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	16	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	0	6	0	0
T20	0	4	0	0
T21	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T2,T3,T18
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	535273251	4072	0	0
CgEnOn_A	535273251	4069	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4072	0	0
T1	244224	0	0	0
T2	103892	3	0	0
T3	348066	9	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	14	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	3425	7	0	0
T20	0	1	0	0
T21	0	4	0	0
T30	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4069	0	0
T1	244224	0	0	0
T2	103892	3	0	0
T3	348066	9	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	14	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	3425	7	0	0
T20	0	1	0	0
T21	0	4	0	0
T30	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T4,T2,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	535273251	4069	0	0
CgEnOn_A	535273251	4066	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4069	0	0
T1	244224	0	0	0
T2	103892	4	0	0
T3	348066	12	0	0
T4	1266	1	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	14	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	0	9	0	0
T20	0	1	0	0
T21	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535273251	4066	0	0
T1	244224	0	0	0
T2	103892	4	0	0
T3	348066	12	0	0
T4	1266	1	0	0
T5	3956	4	0	0
T6	2270	0	0	0
T8	0	14	0	0
T15	3726	0	0	0
T16	2098	0	0	0
T17	2233	5	0	0
T18	1730	1	0	0
T19	0	9	0	0
T20	0	1	0	0
T21	0	5	0	0