Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	666983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4016889

1

T7

8

T8

5

T6

119

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1146129	1			T8	7		T6	10		T26	5
values[0x0]	1624832	1			T7	20		T8	6		T6	102
values[0x1]	1912911	1			T7	21		T8	9		T6	109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	361443	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4322429

1

T7

14

T8

8

T6

144

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18865	1			T8	1		T31	1		T77	1
valid_sources[0x01]	18486	1			T6	1		T5	4		T1	1
valid_sources[0x02]	18677	1			T31	1		T1	2		T2	500
valid_sources[0x03]	18624	1			T8	1		T77	2		T5	2
valid_sources[0x04]	18824	1			T5	6		T1	2		T2	484
valid_sources[0x05]	17618	1			T6	2		T5	1		T1	3
valid_sources[0x06]	18201	1			T26	1		T77	1		T5	5
valid_sources[0x07]	20886	1			T7	1		T26	2		T77	1
valid_sources[0x08]	17073	1			T39	1		T19	10		T2	399
valid_sources[0x09]	18696	1			T6	2		T5	1		T1	2
valid_sources[0x0a]	17969	1			T6	1		T30	1		T5	2
valid_sources[0x0b]	18307	1			T6	1		T34	2		T5	3
valid_sources[0x0c]	18289	1			T77	1		T5	1		T85	1
valid_sources[0x0d]	18353	1			T6	1		T30	1		T77	1
valid_sources[0x0e]	17714	1			T6	1		T5	4		T2	490
valid_sources[0x0f]	18511	1			T6	1		T5	3		T85	1
valid_sources[0x10]	17407	1			T5	3		T1	5		T2	482
valid_sources[0x11]	18415	1			T6	1		T1	1		T2	541
valid_sources[0x12]	19220	1			T6	1		T31	2		T5	1
valid_sources[0x13]	17351	1			T6	1		T39	2		T1	3
valid_sources[0x14]	17507	1			T77	2		T2	492		T3	10
valid_sources[0x15]	17412	1			T6	6		T34	6		T77	1
valid_sources[0x16]	18738	1			T6	1		T5	2		T1	1
valid_sources[0x17]	19042	1			T6	2		T30	1		T5	3
valid_sources[0x18]	20038	1			T7	1		T30	2		T5	1
valid_sources[0x19]	17876	1			T6	4		T26	1		T32	20
valid_sources[0x1a]	19567	1			T6	1		T30	3		T85	1
valid_sources[0x1b]	18363	1			T30	1		T77	1		T85	1
valid_sources[0x1c]	17723	1			T7	1		T30	1		T5	1
valid_sources[0x1d]	18670	1			T5	2		T2	440		T3	8
valid_sources[0x1e]	18991	1			T7	3		T8	1		T6	1
valid_sources[0x1f]	17067	1			T31	3		T77	1		T5	1
valid_sources[0x20]	18830	1			T29	1		T5	1		T1	1
valid_sources[0x21]	17607	1			T6	1		T5	3		T2	453
valid_sources[0x22]	18143	1			T6	3		T5	6		T85	1
valid_sources[0x23]	17957	1			T6	1		T26	1		T85	2
valid_sources[0x24]	18555	1			T6	1		T30	2		T5	1
valid_sources[0x25]	17964	1			T6	1		T77	4		T5	3
valid_sources[0x26]	17986	1			T6	1		T5	2		T1	1
valid_sources[0x27]	19489	1			T6	1		T5	3		T39	2
valid_sources[0x28]	18893	1			T6	2		T5	1		T1	1
valid_sources[0x29]	18424	1			T6	1		T77	1		T5	2
valid_sources[0x2a]	19177	1			T6	1		T77	1		T1	1
valid_sources[0x2b]	17435	1			T77	1		T5	2		T1	4
valid_sources[0x2c]	18161	1			T6	2		T5	2		T1	3
valid_sources[0x2d]	18855	1			T5	3		T2	439		T3	7
valid_sources[0x2e]	17933	1			T6	2		T29	2		T5	2
valid_sources[0x2f]	19429	1			T29	3		T5	2		T1	5
valid_sources[0x30]	17206	1			T8	1		T77	1		T5	3
valid_sources[0x31]	18482	1			T6	1		T5	2		T1	2
valid_sources[0x32]	19356	1			T6	1		T5	2		T1	3
valid_sources[0x33]	17102	1			T5	7		T1	2		T2	529
valid_sources[0x34]	18537	1			T6	3		T1	2		T2	423
valid_sources[0x35]	17799	1			T6	1		T5	2		T40	1
valid_sources[0x36]	19038	1			T5	5		T85	1		T39	1
valid_sources[0x37]	18810	1			T7	2		T8	1		T6	1
valid_sources[0x38]	17048	1			T6	1		T5	1		T2	500
valid_sources[0x39]	17209	1			T6	1		T30	2		T34	1
valid_sources[0x3a]	19815	1			T6	1		T29	8		T5	2
valid_sources[0x3b]	18333	1			T5	3		T1	3		T2	517
valid_sources[0x3c]	17696	1			T6	3		T5	3		T39	1
valid_sources[0x3d]	18152	1			T6	1		T26	1		T5	4
valid_sources[0x3e]	18360	1			T7	1		T29	1		T77	4
valid_sources[0x3f]	17656	1			T6	4		T77	1		T5	1
valid_sources[0x40]	17921	1			T6	1		T30	1		T5	1
valid_sources[0x41]	18697	1			T5	3		T85	1		T1	2
valid_sources[0x42]	18224	1			T6	2		T5	1		T85	1
valid_sources[0x43]	19241	1			T5	1		T1	5		T2	473
valid_sources[0x44]	18859	1			T6	3		T77	2		T5	1
valid_sources[0x45]	17964	1			T8	1		T40	4		T1	3
valid_sources[0x46]	19233	1			T6	1		T5	1		T1	2
valid_sources[0x47]	17691	1			T26	1		T77	3		T5	5
valid_sources[0x48]	19074	1			T6	1		T26	1		T40	1
valid_sources[0x49]	17361	1			T6	1		T32	14		T5	1
valid_sources[0x4a]	19917	1			T6	1		T5	2		T40	1
valid_sources[0x4b]	18124	1			T6	1		T1	1		T2	440
valid_sources[0x4c]	16540	1			T7	2		T6	1		T5	4
valid_sources[0x4d]	19425	1			T7	3		T31	2		T77	1
valid_sources[0x4e]	16883	1			T30	1		T31	2		T34	2
valid_sources[0x4f]	19474	1			T6	1		T30	1		T31	3
valid_sources[0x50]	15760	1			T5	3		T1	2		T2	438
valid_sources[0x51]	18484	1			T5	1		T1	1		T2	451
valid_sources[0x52]	18565	1			T31	3		T5	1		T1	3
valid_sources[0x53]	18080	1			T6	3		T1	1		T2	487
valid_sources[0x54]	19288	1			T34	1		T5	4		T39	1
valid_sources[0x55]	17950	1			T6	1		T5	4		T2	455
valid_sources[0x56]	18577	1			T5	3		T85	1		T1	2
valid_sources[0x57]	18007	1			T7	1		T5	4		T85	1
valid_sources[0x58]	18393	1			T5	3		T1	1		T2	453
valid_sources[0x59]	18579	1			T6	2		T5	4		T1	3
valid_sources[0x5a]	18138	1			T6	2		T26	1		T32	7
valid_sources[0x5b]	18618	1			T6	1		T27	140		T5	2
valid_sources[0x5c]	17927	1			T30	1		T5	6		T1	6
valid_sources[0x5d]	17817	1			T6	1		T34	2		T5	1
valid_sources[0x5e]	18856	1			T6	1		T5	6		T1	1
valid_sources[0x5f]	18248	1			T6	1		T5	3		T1	4
valid_sources[0x60]	18046	1			T6	1		T26	1		T5	3
valid_sources[0x61]	17404	1			T6	1		T30	1		T5	2
valid_sources[0x62]	18151	1			T77	2		T5	4		T40	1
valid_sources[0x63]	18986	1			T5	6		T1	3		T2	471
valid_sources[0x64]	18192	1			T7	1		T5	2		T85	1
valid_sources[0x65]	19026	1			T6	1		T1	2		T2	464
valid_sources[0x66]	17948	1			T7	1		T77	1		T5	5
valid_sources[0x67]	18252	1			T6	1		T5	1		T1	1
valid_sources[0x68]	18129	1			T7	2		T8	1		T6	1
valid_sources[0x69]	17368	1			T6	2		T5	1		T1	1
valid_sources[0x6a]	19331	1			T30	1		T5	5		T1	1
valid_sources[0x6b]	17732	1			T5	3		T1	1		T2	467
valid_sources[0x6c]	18632	1			T6	1		T30	1		T5	2
valid_sources[0x6d]	17989	1			T26	1		T5	4		T40	1
valid_sources[0x6e]	18244	1			T8	1		T5	2		T85	1
valid_sources[0x6f]	17557	1			T5	3		T1	2		T2	462
valid_sources[0x70]	19694	1			T5	2		T1	1		T2	454
valid_sources[0x71]	18842	1			T8	1		T2	479		T3	1
valid_sources[0x72]	18856	1			T6	1		T5	1		T40	1
valid_sources[0x73]	18521	1			T30	2		T31	2		T5	2
valid_sources[0x74]	19004	1			T6	1		T5	6		T1	3
valid_sources[0x75]	17877	1			T5	5		T1	1		T2	465
valid_sources[0x76]	17159	1			T6	3		T77	1		T5	1
valid_sources[0x77]	18749	1			T6	1		T1	3		T2	522
valid_sources[0x78]	18113	1			T6	1		T5	3		T1	1
valid_sources[0x79]	18490	1			T8	1		T6	1		T5	2
valid_sources[0x7a]	18444	1			T6	2		T5	1		T1	1
valid_sources[0x7b]	18588	1			T6	2		T5	5		T1	3
valid_sources[0x7c]	18151	1			T30	1		T1	3		T2	468
valid_sources[0x7d]	17780	1			T6	3		T85	1		T1	3
valid_sources[0x7e]	19283	1			T5	1		T1	2		T2	439
valid_sources[0x7f]	17453	1			T34	1		T77	5		T5	4
valid_sources[0x80]	19165	1			T31	3		T85	1		T2	510

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1010700

1

T8

2

T6

8

T26

2

values[0x0]

all_enables

biggest_size

1526809

1

T7

3

T8

2

T6

62

values[0x1]

all_enables

biggest_size

1479380

1

T7

5

T8

1

T6

49