Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T38
0	1	Covered	T7,T2,T3
1	0	Covered	T7,T8,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T4
1	0	Covered	T38,T20,T45
1	1	Covered	T7,T8,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	976099911	15358	0	0
GateOpen_A	976099911	22070	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976099911	15358	0	0
T2	0	530	0	0
T3	0	13	0	0
T6	225786	0	0	0
T7	4407	37	0	0
T8	12915	0	0	0
T20	0	9	0	0
T25	0	148	0	0
T26	5826	0	0	0
T27	8583	0	0	0
T28	2681	0	0	0
T29	19923	0	0	0
T30	34591	0	0	0
T31	4624	4	0	0
T32	19525	0	0	0
T38	0	9	0	0
T87	0	60	0	0
T97	0	4	0	0
T99	0	26	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	976099911	22070	0	0
T4	0	12	0	0
T5	0	48	0	0
T6	225786	4	0	0
T7	4407	41	0	0
T8	12915	0	0	0
T26	5826	0	0	0
T27	8583	0	0	0
T28	2681	4	0	0
T29	19923	0	0	0
T30	34591	0	0	0
T31	4624	4	0	0
T32	19525	4	0	0
T34	0	4	0	0
T38	0	13	0	0
T77	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T38
0	1	Covered	T7,T2,T3
1	0	Covered	T7,T8,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T4
1	0	Covered	T38,T20,T45
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	107563027	3614	0	0
GateOpen_A	107563027	5291	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107563027	3614	0	0
T2	0	126	0	0
T3	0	3	0	0
T6	24443	0	0	0
T7	479	9	0	0
T8	1532	0	0	0
T20	0	2	0	0
T25	0	34	0	0
T26	660	0	0	0
T27	936	0	0	0
T28	287	0	0	0
T29	2426	0	0	0
T30	3826	0	0	0
T31	492	1	0	0
T32	2350	0	0	0
T38	0	2	0	0
T87	0	15	0	0
T97	0	1	0	0
T99	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107563027	5291	0	0
T4	0	3	0	0
T5	0	12	0	0
T6	24443	1	0	0
T7	479	10	0	0
T8	1532	0	0	0
T26	660	0	0	0
T27	936	0	0	0
T28	287	1	0	0
T29	2426	0	0	0
T30	3826	0	0	0
T31	492	1	0	0
T32	2350	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T38
0	1	Covered	T7,T2,T3
1	0	Covered	T7,T8,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T4
1	0	Covered	T38,T20,T45
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	215126979	3917	0	0
GateOpen_A	215126979	5594	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126979	3917	0	0
T2	0	136	0	0
T3	0	4	0	0
T6	48886	0	0	0
T7	958	10	0	0
T8	3066	0	0	0
T20	0	2	0	0
T25	0	38	0	0
T26	1320	0	0	0
T27	1872	0	0	0
T28	573	0	0	0
T29	4853	0	0	0
T30	7651	0	0	0
T31	983	1	0	0
T32	4701	0	0	0
T38	0	2	0	0
T87	0	15	0	0
T97	0	1	0	0
T99	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126979	5594	0	0
T4	0	3	0	0
T5	0	12	0	0
T6	48886	1	0	0
T7	958	11	0	0
T8	3066	0	0	0
T26	1320	0	0	0
T27	1872	0	0	0
T28	573	1	0	0
T29	4853	0	0	0
T30	7651	0	0	0
T31	983	1	0	0
T32	4701	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T38
0	1	Covered	T7,T2,T3
1	0	Covered	T7,T8,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T4
1	0	Covered	T38,T20,T45
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	431856273	3955	0	0
GateOpen_A	431856273	5634	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431856273	3955	0	0
T2	0	136	0	0
T3	0	3	0	0
T6	97796	0	0	0
T7	1980	8	0	0
T8	5544	0	0	0
T20	0	2	0	0
T25	0	38	0	0
T26	2564	0	0	0
T27	3850	0	0	0
T28	1214	0	0	0
T29	8429	0	0	0
T30	15409	0	0	0
T31	2099	1	0	0
T32	8316	0	0	0
T38	0	2	0	0
T87	0	16	0	0
T97	0	1	0	0
T99	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431856273	5634	0	0
T4	0	3	0	0
T5	0	12	0	0
T6	97796	1	0	0
T7	1980	9	0	0
T8	5544	0	0	0
T26	2564	0	0	0
T27	3850	0	0	0
T28	1214	1	0	0
T29	8429	0	0	0
T30	15409	0	0	0
T31	2099	1	0	0
T32	8316	1	0	0
T34	0	1	0	0
T38	0	3	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T31,T38
0	1	Covered	T7,T2,T3
1	0	Covered	T7,T8,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T31,T4
1	0	Covered	T38,T20,T45
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	221553632	3872	0	0
GateOpen_A	221553632	5551	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553632	3872	0	0
T2	0	132	0	0
T3	0	3	0	0
T6	54661	0	0	0
T7	990	10	0	0
T8	2773	0	0	0
T20	0	3	0	0
T25	0	38	0	0
T26	1282	0	0	0
T27	1925	0	0	0
T28	607	0	0	0
T29	4215	0	0	0
T30	7705	0	0	0
T31	1050	1	0	0
T32	4158	0	0	0
T38	0	3	0	0
T87	0	14	0	0
T97	0	1	0	0
T99	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553632	5551	0	0
T4	0	3	0	0
T5	0	12	0	0
T6	54661	1	0	0
T7	990	11	0	0
T8	2773	0	0	0
T26	1282	0	0	0
T27	1925	0	0	0
T28	607	1	0	0
T29	4215	0	0	0
T30	7705	0	0	0
T31	1050	1	0	0
T32	4158	1	0	0
T34	0	1	0	0
T38	0	4	0	0
T77	0	1	0	0