Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	845667845	77867	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	845667845	77867	0	0
T1	243710	148	0	0
T2	2376995	1010	0	0
T3	520360	286	0	0
T12	0	136	0	0
T13	0	931	0	0
T14	0	298	0	0
T15	0	767	0	0
T16	0	42	0	0
T17	0	620	0	0
T18	0	265	0	0
T19	11690	0	0	0
T20	4745	0	0	0
T21	6635	0	0	0
T22	5110	0	0	0
T23	6105	0	0	0
T24	64210	0	0	0
T25	432590	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169133569	11531	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	11531	0	0
T1	48742	25	0	0
T2	475399	162	0	0
T3	104072	49	0	0
T12	0	22	0	0
T13	0	120	0	0
T14	0	38	0	0
T15	0	113	0	0
T16	0	8	0	0
T17	0	92	0	0
T18	0	42	0	0
T19	2338	0	0	0
T20	949	0	0	0
T21	1327	0	0	0
T22	1022	0	0	0
T23	1221	0	0	0
T24	12842	0	0	0
T25	86518	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169133569	11413	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	11413	0	0
T1	48742	24	0	0
T2	475399	161	0	0
T3	104072	49	0	0
T12	0	21	0	0
T13	0	119	0	0
T14	0	39	0	0
T15	0	95	0	0
T16	0	8	0	0
T17	0	78	0	0
T18	0	42	0	0
T19	2338	0	0	0
T20	949	0	0	0
T21	1327	0	0	0
T22	1022	0	0	0
T23	1221	0	0	0
T24	12842	0	0	0
T25	86518	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169133569	15674	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	15674	0	0
T1	48742	30	0	0
T2	475399	204	0	0
T3	104072	57	0	0
T12	0	27	0	0
T13	0	187	0	0
T14	0	59	0	0
T15	0	154	0	0
T16	0	8	0	0
T17	0	122	0	0
T18	0	54	0	0
T19	2338	0	0	0
T20	949	0	0	0
T21	1327	0	0	0
T22	1022	0	0	0
T23	1221	0	0	0
T24	12842	0	0	0
T25	86518	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169133569	15586	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	15586	0	0
T1	48742	29	0	0
T2	475399	204	0	0
T3	104072	57	0	0
T12	0	27	0	0
T13	0	189	0	0
T14	0	60	0	0
T15	0	156	0	0
T16	0	8	0	0
T17	0	124	0	0
T18	0	54	0	0
T19	2338	0	0	0
T20	949	0	0	0
T21	1327	0	0	0
T22	1022	0	0	0
T23	1221	0	0	0
T24	12842	0	0	0
T25	86518	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169133569	23663	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	23663	0	0
T1	48742	40	0	0
T2	475399	279	0	0
T3	104072	74	0	0
T12	0	39	0	0
T13	0	316	0	0
T14	0	102	0	0
T15	0	249	0	0
T16	0	10	0	0
T17	0	204	0	0
T18	0	73	0	0
T19	2338	0	0	0
T20	949	0	0	0
T21	1327	0	0	0
T22	1022	0	0	0
T23	1221	0	0	0
T24	12842	0	0	0
T25	86518	0	0	0