Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T4,T5,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	169133569	166100341	0	0
AllClkBypReqTrue_A	169133569	139797	0	0
IoClkBypReqFalse_A	169133569	166013943	0	2415
IoClkBypReqTrue_A	169133569	221445	0	0
LcClkBypAckFalse_A	169133569	166109407	0	0
LcClkBypAckTrue_A	169133569	130731	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	166100341	0	0
T6	12586	12573	0	0
T7	2022	1925	0	0
T8	1096	932	0	0
T26	1282	1178	0	0
T27	3770	3637	0	0
T28	1253	1056	0	0
T29	1228	998	0	0
T30	1766	1737	0	0
T31	2186	1973	0	0
T32	2165	1823	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	139797	0	0
T2	0	5108	0	0
T6	12586	0	0	0
T8	1096	126	0	0
T19	0	66	0	0
T21	0	39	0	0
T26	1282	36	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	200	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	288	0	0
T34	1928	116	0	0
T77	0	265	0	0
T85	0	77	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	166013943	0	2415
T6	12586	12571	0	3
T7	2022	1923	0	3
T8	1096	865	0	3
T26	1282	1119	0	3
T27	3770	3635	0	3
T28	1253	1010	0	3
T29	1228	925	0	3
T30	1766	1735	0	3
T31	2186	1971	0	3
T32	2165	1735	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	221445	0	0
T6	12586	0	0	0
T8	1096	191	0	0
T19	0	38	0	0
T21	0	225	0	0
T26	1282	93	0	0
T27	3770	0	0	0
T28	1253	44	0	0
T29	1228	271	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	374	0	0
T34	1928	293	0	0
T77	0	479	0	0
T85	0	32	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	166109407	0	0
T6	12586	12573	0	0
T7	2022	1925	0	0
T8	1096	933	0	0
T26	1282	1126	0	0
T27	3770	3637	0	0
T28	1253	1030	0	0
T29	1228	1015	0	0
T30	1766	1737	0	0
T31	2186	1973	0	0
T32	2165	1864	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	130731	0	0
T6	12586	0	0	0
T8	1096	125	0	0
T19	0	34	0	0
T21	0	136	0	0
T26	1282	88	0	0
T27	3770	0	0	0
T28	1253	26	0	0
T29	1228	183	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	247	0	0
T34	1928	147	0	0
T77	0	145	0	0
T85	0	27	0	0