Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1844806896	15917	0	0
TransStop_A	1844806896	8193	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1844806896	15917	0	0
T2	0	253	0	0
T3	0	39	0	0
T4	75284	0	0	0
T25	0	88	0	0
T27	16040	35	0	0
T28	5064	0	0	0
T29	35120	0	0	0
T30	64204	9	0	0
T31	8748	4	0	0
T32	34652	0	0	0
T34	15740	0	0	0
T38	6412	0	0	0
T77	40220	0	0	0
T86	0	42	0	0
T97	0	4	0	0
T98	0	26	0	0
T101	0	35	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1844806896	8193	0	0
T2	0	114	0	0
T3	0	18	0	0
T4	75284	0	0	0
T25	0	49	0	0
T27	16040	11	0	0
T28	5064	0	0	0
T29	35120	0	0	0
T30	64204	2	0	0
T31	8748	4	0	0
T32	34652	0	0	0
T34	15740	0	0	0
T38	6412	0	0	0
T77	40220	0	0	0
T86	0	23	0	0
T97	0	4	0	0
T98	0	18	0	0
T101	0	18	0	0
T125	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	461201724	4014	0	0
TransStop_A	461201724	2034	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	4014	0	0
T2	0	61	0	0
T3	0	8	0	0
T4	18821	0	0	0
T25	0	21	0	0
T27	4010	10	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	3	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	11	0	0
T97	0	1	0	0
T98	0	7	0	0
T101	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	2034	0	0
T2	0	28	0	0
T3	0	3	0	0
T4	18821	0	0	0
T25	0	11	0	0
T27	4010	2	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	0	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	6	0	0
T97	0	1	0	0
T98	0	4	0	0
T101	0	3	0	0
T125	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	461201724	3871	0	0
TransStop_A	461201724	1986	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	3871	0	0
T2	0	63	0	0
T3	0	10	0	0
T4	18821	0	0	0
T25	0	20	0	0
T27	4010	7	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	1	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	10	0	0
T97	0	1	0	0
T98	0	4	0	0
T101	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	1986	0	0
T2	0	29	0	0
T3	0	5	0	0
T4	18821	0	0	0
T25	0	11	0	0
T27	4010	2	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	0	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	6	0	0
T97	0	1	0	0
T98	0	4	0	0
T101	0	4	0	0
T125	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	461201724	4031	0	0
TransStop_A	461201724	2096	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	4031	0	0
T2	0	69	0	0
T3	0	10	0	0
T4	18821	0	0	0
T25	0	23	0	0
T27	4010	8	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	2	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	10	0	0
T97	0	1	0	0
T98	0	7	0	0
T101	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	2096	0	0
T2	0	32	0	0
T3	0	5	0	0
T4	18821	0	0	0
T25	0	14	0	0
T27	4010	3	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	1	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	6	0	0
T97	0	1	0	0
T98	0	4	0	0
T101	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	461201724	4001	0	0
TransStop_A	461201724	2077	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	4001	0	0
T2	0	60	0	0
T3	0	11	0	0
T4	18821	0	0	0
T25	0	24	0	0
T27	4010	10	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	3	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	11	0	0
T97	0	1	0	0
T98	0	8	0	0
T101	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201724	2077	0	0
T2	0	25	0	0
T3	0	5	0	0
T4	18821	0	0	0
T25	0	13	0	0
T27	4010	4	0	0
T28	1266	0	0	0
T29	8780	0	0	0
T30	16051	1	0	0
T31	2187	1	0	0
T32	8663	0	0	0
T34	3935	0	0	0
T38	1603	0	0	0
T77	10055	0	0	0
T86	0	5	0	0
T97	0	1	0	0
T98	0	6	0	0
T101	0	6	0	0