Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_io_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_all_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_byp_req

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T6	1185460	1184112	0	0
T7	28212	27002	0	0
T8	66830	64859	0	0
T26	32840	31333	0	0
T27	54404	52708	0	0
T28	17285	14777	0	0
T29	101052	98865	0	0
T30	178422	175806	0	0
T31	29900	27244	0	0
T32	102217	99962	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	169133569	166242513	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	166242513	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	169133569	166242513	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	166242513	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	169133569	166242513	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	166242513	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	107562629	107020635	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	107020635	0	0
T6	24443	24419	0	0
T7	479	472	0	0
T8	1532	1518	0	0
T26	659	652	0	0
T27	936	929	0	0
T28	287	266	0	0
T29	2425	2398	0	0
T30	3825	3791	0	0
T31	491	474	0	0
T32	2350	2322	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	461201266	456550196	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	456550196	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	221553224	219318802	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553224	219318802	0	0
T6	54661	54600	0	0
T7	989	943	0	0
T8	2772	2677	0	0
T26	1282	1215	0	0
T27	1925	1858	0	0
T28	607	513	0	0
T29	4214	4112	0	0
T30	7704	7582	0	0
T31	1049	947	0	0
T32	4158	4057	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	431855825	427458396	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431855825	427458396	0	0
T6	97796	97675	0	0
T7	1980	1887	0	0
T8	5544	5355	0	0
T26	2564	2429	0	0
T27	3849	3714	0	0
T28	1214	1025	0	0
T29	8428	8225	0	0
T30	15408	15163	0	0
T31	2099	1896	0	0
T32	8316	8113	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	215126538	214042404	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126538	214042404	0	0
T6	48886	48838	0	0
T7	957	943	0	0
T8	3066	3039	0	0
T26	1320	1306	0	0
T27	1871	1857	0	0
T28	573	532	0	0
T29	4852	4797	0	0
T30	7650	7581	0	0
T31	983	948	0	0
T32	4701	4646	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	107562629	107020635	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	107020635	0	0
T6	24443	24419	0	0
T7	479	472	0	0
T8	1532	1518	0	0
T26	659	652	0	0
T27	936	929	0	0
T28	287	266	0	0
T29	2425	2398	0	0
T30	3825	3791	0	0
T31	491	474	0	0
T32	2350	2322	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	461201266	456550196	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	456550196	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	107562629	107020635	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	107020635	0	0
T6	24443	24419	0	0
T7	479	472	0	0
T8	1532	1518	0	0
T26	659	652	0	0
T27	936	929	0	0
T28	287	266	0	0
T29	2425	2398	0	0
T30	3825	3791	0	0
T31	491	474	0	0
T32	2350	2322	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	107562629	107020635	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	107020635	0	0
T6	24443	24419	0	0
T7	479	472	0	0
T8	1532	1518	0	0
T26	659	652	0	0
T27	936	929	0	0
T28	287	266	0	0
T29	2425	2398	0	0
T30	3825	3791	0	0
T31	491	474	0	0
T32	2350	2322	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	215126538	214042404	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126538	214042404	0	0
T6	48886	48838	0	0
T7	957	943	0	0
T8	3066	3039	0	0
T26	1320	1306	0	0
T27	1871	1857	0	0
T28	573	532	0	0
T29	4852	4797	0	0
T30	7650	7581	0	0
T31	983	948	0	0
T32	4701	4646	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	431855825	427458396	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431855825	427458396	0	0
T6	97796	97675	0	0
T7	1980	1887	0	0
T8	5544	5355	0	0
T26	2564	2429	0	0
T27	3849	3714	0	0
T28	1214	1025	0	0
T29	8428	8225	0	0
T30	15408	15163	0	0
T31	2099	1896	0	0
T32	8316	8113	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	221553224	219318802	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553224	219318802	0	0
T6	54661	54600	0	0
T7	989	943	0	0
T8	2772	2677	0	0
T26	1282	1215	0	0
T27	1925	1858	0	0
T28	607	513	0	0
T29	4214	4112	0	0
T30	7704	7582	0	0
T31	1049	947	0	0
T32	4158	4057	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	461201266	456550196	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	456550196	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	461201266	456550196	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	456550196	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	461201266	456550196	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	456550196	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	461201266	456550196	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	456550196	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0