Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	170052143	5923399	0	0
clk_enables_rd_A	170052143	36566	0	0
clk_hints_rd_A	170052143	32537	0	0
extclk_ctrl_rd_A	170052143	41527	0	0
extclk_ctrl_regwen_rd_A	170052143	31040	0	0
jitter_enable_rd_A	170052143	44793	0	0
jitter_regwen_rd_A	170052143	34666	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	5923399	0	0
T2	475399	166781	0	0
T3	104072	0	0	0
T13	0	158300	0	0
T15	0	126180	0	0
T17	0	48819	0	0
T18	0	108578	0	0
T22	1022	0	0	0
T23	1221	0	0	0
T24	12842	0	0	0
T25	86518	0	0	0
T42	0	248377	0	0
T52	0	52032	0	0
T78	0	75752	0	0
T79	0	68864	0	0
T80	0	118913	0	0
T81	1792	0	0	0
T82	1190	0	0	0
T83	2249	0	0	0
T84	980	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	36566	0	0
T14	775322	2	0	0
T15	259349	0	0	0
T16	23915	0	0	0
T17	0	1805	0	0
T33	10310	0	0	0
T78	0	3041	0	0
T80	0	4567	0	0
T127	0	3	0	0
T148	0	1	0	0
T149	0	15	0	0
T150	0	3	0	0
T151	0	8	0	0
T152	0	13	0	0
T153	1618	0	0	0
T154	2088	0	0	0
T155	1187	0	0	0
T156	115333	0	0	0
T157	1343	0	0	0
T158	1991	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	32537	0	0
T14	0	3	0	0
T17	0	1724	0	0
T37	306553	0	0	0
T78	0	2741	0	0
T80	0	3864	0	0
T148	0	3	0	0
T149	0	10	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	17	0	0
T159	1590	7	0	0
T160	1657	0	0	0
T161	52800	0	0	0
T162	2711	0	0	0
T163	1489	0	0	0
T164	941	0	0	0
T165	1312	0	0	0
T166	1253	0	0	0
T167	1944	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	41527	0	0
T1	48742	0	0	0
T4	4704	9	0	0
T5	71160	99	0	0
T14	0	194	0	0
T17	0	2095	0	0
T21	0	15	0	0
T35	13200	0	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T60	0	28	0	0
T77	2513	46	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T164	0	3	0	0
T168	0	49	0	0
T169	0	37	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	31040	0	0
T1	48742	0	0	0
T4	4704	5	0	0
T5	71160	39	0	0
T17	0	1589	0	0
T35	13200	0	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T77	2513	0	0	0
T78	0	2229	0	0
T80	0	3743	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T124	0	25	0	0
T170	0	3	0	0
T171	0	40	0	0
T172	0	20	0	0
T173	0	26	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	44793	0	0
T14	0	98	0	0
T17	0	2307	0	0
T37	306553	0	0	0
T78	0	2943	0	0
T80	0	5568	0	0
T127	0	117	0	0
T148	0	89	0	0
T149	0	354	0	0
T150	0	97	0	0
T159	1590	59	0	0
T160	1657	0	0	0
T161	52800	0	0	0
T162	2711	0	0	0
T163	1489	0	0	0
T164	941	0	0	0
T165	1312	0	0	0
T166	1253	0	0	0
T167	1944	0	0	0
T174	0	81	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	34666	0	0
T17	164697	1857	0	0
T60	1639	0	0	0
T61	1772	0	0	0
T62	74120	0	0	0
T63	46178	0	0	0
T64	750	0	0	0
T65	1224	0	0	0
T78	0	2697	0	0
T80	0	4274	0	0
T175	0	3175	0	0
T176	0	2689	0	0
T177	0	5055	0	0
T178	0	3826	0	0
T179	0	1190	0	0
T180	0	1809	0	0
T181	0	6156	0	0
T182	1584	0	0	0
T183	1597	0	0	0
T184	1825	0	0	0