Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	507400707	412	0	0
StatusRise_A	507400707	412	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507400707	412	0	0
T4	14112	0	0	0
T5	213480	0	0	0
T20	0	7	0	0
T35	39600	0	0	0
T38	5001	6	0	0
T39	3885	0	0	0
T40	5019	0	0	0
T41	2352	0	0	0
T45	0	12	0	0
T65	0	9	0	0
T77	7539	0	0	0
T85	4998	0	0	0
T86	9186	0	0	0
T185	0	3	0	0
T186	0	3	0	0
T187	0	11	0	0
T188	0	16	0	0
T189	0	9	0	0
T190	0	13	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507400707	412	0	0
T4	14112	0	0	0
T5	213480	0	0	0
T20	0	7	0	0
T35	39600	0	0	0
T38	5001	6	0	0
T39	3885	0	0	0
T40	5019	0	0	0
T41	2352	0	0	0
T45	0	12	0	0
T65	0	9	0	0
T77	7539	0	0	0
T85	4998	0	0	0
T86	9186	0	0	0
T185	0	3	0	0
T186	0	3	0	0
T187	0	11	0	0
T188	0	16	0	0
T189	0	9	0	0
T190	0	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	169133569	135	0	0
StatusRise_A	169133569	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	135	0	0
T4	4704	0	0	0
T5	71160	0	0	0
T20	0	2	0	0
T35	13200	0	0	0
T38	1667	1	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T45	0	4	0	0
T65	0	4	0	0
T77	2513	0	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	135	0	0
T4	4704	0	0	0
T5	71160	0	0	0
T20	0	2	0	0
T35	13200	0	0	0
T38	1667	1	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T45	0	4	0	0
T65	0	4	0	0
T77	2513	0	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	169133569	142	0	0
StatusRise_A	169133569	142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	142	0	0
T4	4704	0	0	0
T5	71160	0	0	0
T20	0	2	0	0
T35	13200	0	0	0
T38	1667	2	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2513	0	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T189	0	4	0	0
T190	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	142	0	0
T4	4704	0	0	0
T5	71160	0	0	0
T20	0	2	0	0
T35	13200	0	0	0
T38	1667	2	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2513	0	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T189	0	4	0	0
T190	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	169133569	135	0	0
StatusRise_A	169133569	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	135	0	0
T4	4704	0	0	0
T5	71160	0	0	0
T20	0	3	0	0
T35	13200	0	0	0
T38	1667	3	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T45	0	3	0	0
T65	0	4	0	0
T77	2513	0	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	5	0	0
T188	0	6	0	0
T189	0	2	0	0
T190	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169133569	135	0	0
T4	4704	0	0	0
T5	71160	0	0	0
T20	0	3	0	0
T35	13200	0	0	0
T38	1667	3	0	0
T39	1295	0	0	0
T40	1673	0	0	0
T41	784	0	0	0
T45	0	3	0	0
T65	0	4	0	0
T77	2513	0	0	0
T85	1666	0	0	0
T86	3062	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	5	0	0
T188	0	6	0	0
T189	0	2	0	0
T190	0	5	0	0