Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Covered	T7,T8,T6
1	1	Covered	T7,T8,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51280	0	0
CgEnOn_A	2147483647	41762	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51280	0	0
T4	52155	0	0	0
T5	138708	0	0	0
T6	171125	3	0	0
T7	3416	50	0	0
T8	10142	3	0	0
T18	0	5	0	0
T20	0	12	0	0
T26	4543	3	0	0
T27	10666	13	0	0
T28	3339	3	0	0
T29	24485	3	0	0
T30	42933	6	0	0
T31	5759	7	0	0
T32	24029	3	0	0
T34	3935	0	0	0
T35	75011	0	0	0
T38	5018	11	0	0
T39	15487	0	0	0
T40	3551	0	0	0
T41	6916	0	0	0
T45	0	25	0	0
T65	0	5	0	0
T77	32629	0	0	0
T85	14912	0	0	0
T86	26296	11	0	0
T185	0	5	0	0
T186	0	5	0	0
T187	0	15	0	0
T188	0	30	0	0
T191	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41762	0	0
T2	0	645	0	0
T3	0	21	0	0
T4	52155	0	0	0
T5	138708	0	0	0
T6	171125	0	0	0
T7	3416	47	0	0
T8	10142	0	0	0
T18	0	4	0	0
T20	0	18	0	0
T25	0	189	0	0
T26	4543	0	0	0
T27	10666	10	0	0
T28	3339	0	0	0
T29	24485	0	0	0
T30	42933	0	0	0
T31	5759	4	0	0
T32	24029	0	0	0
T34	3935	0	0	0
T35	75011	0	0	0
T38	5018	17	0	0
T39	15487	0	0	0
T40	3551	0	0	0
T41	6916	0	0	0
T45	0	25	0	0
T65	0	5	0	0
T77	32629	0	0	0
T85	14912	0	0	0
T86	26296	0	0	0
T87	0	57	0	0
T97	0	4	0	0
T99	0	29	0	0
T185	0	5	0	0
T186	0	5	0	0
T187	0	15	0	0
T188	0	30	0	0
T189	0	4	0	0
T190	0	4	0	0
T191	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	215126538	151	0	0
CgEnOn_A	215126538	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126538	151	0	0
T4	6108	0	0	0
T5	21329	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	16639	0	0	0
T38	735	2	0	0
T39	3430	0	0	0
T40	771	0	0	0
T41	1510	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	5170	0	0	0
T85	3406	0	0	0
T86	5814	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126538	151	0	0
T4	6108	0	0	0
T5	21329	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	16639	0	0	0
T38	735	2	0	0
T39	3430	0	0	0
T40	771	0	0	0
T41	1510	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	5170	0	0	0
T85	3406	0	0	0
T86	5814	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107562629	151	0	0
CgEnOn_A	107562629	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	151	0	0
T4	3053	0	0	0
T5	10663	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	8320	0	0	0
T38	368	2	0	0
T39	1715	0	0	0
T40	386	0	0	0
T41	755	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2584	0	0	0
T85	1702	0	0	0
T86	2907	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	151	0	0
T4	3053	0	0	0
T5	10663	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	8320	0	0	0
T38	368	2	0	0
T39	1715	0	0	0
T40	386	0	0	0
T41	755	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2584	0	0	0
T85	1702	0	0	0
T86	2907	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107562629	151	0	0
CgEnOn_A	107562629	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	151	0	0
T4	3053	0	0	0
T5	10663	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	8320	0	0	0
T38	368	2	0	0
T39	1715	0	0	0
T40	386	0	0	0
T41	755	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2584	0	0	0
T85	1702	0	0	0
T86	2907	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	151	0	0
T4	3053	0	0	0
T5	10663	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	8320	0	0	0
T38	368	2	0	0
T39	1715	0	0	0
T40	386	0	0	0
T41	755	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2584	0	0	0
T85	1702	0	0	0
T86	2907	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107562629	151	0	0
CgEnOn_A	107562629	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	151	0	0
T4	3053	0	0	0
T5	10663	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	8320	0	0	0
T38	368	2	0	0
T39	1715	0	0	0
T40	386	0	0	0
T41	755	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2584	0	0	0
T85	1702	0	0	0
T86	2907	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	151	0	0
T4	3053	0	0	0
T5	10663	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	8320	0	0	0
T38	368	2	0	0
T39	1715	0	0	0
T40	386	0	0	0
T41	755	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	2584	0	0	0
T85	1702	0	0	0
T86	2907	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431855825	151	0	0
CgEnOn_A	431855825	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431855825	151	0	0
T4	18067	0	0	0
T5	85390	0	0	0
T18	0	1	0	0
T20	0	2	0	0
T35	33412	0	0	0
T38	1577	2	0	0
T39	6912	0	0	0
T40	1622	0	0	0
T41	3141	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	9653	0	0	0
T85	6400	0	0	0
T86	11761	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T191	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431855825	142	0	0
T4	18067	0	0	0
T5	85390	0	0	0
T20	0	2	0	0
T35	33412	0	0	0
T38	1577	2	0	0
T39	6912	0	0	0
T40	1622	0	0	0
T41	3141	0	0	0
T45	0	5	0	0
T65	0	1	0	0
T77	9653	0	0	0
T85	6400	0	0	0
T86	11761	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	6	0	0
T189	0	4	0	0
T190	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461201266	140	0	0
CgEnOn_A	461201266	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	140	0	0
T4	18821	0	0	0
T5	88951	0	0	0
T20	0	2	0	0
T35	52804	0	0	0
T38	1602	1	0	0
T39	7200	0	0	0
T40	1689	0	0	0
T41	3272	0	0	0
T45	0	4	0	0
T65	0	4	0	0
T77	10054	0	0	0
T85	6668	0	0	0
T86	12252	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	136	0	0
T4	18821	0	0	0
T5	88951	0	0	0
T20	0	2	0	0
T35	52804	0	0	0
T38	1602	1	0	0
T39	7200	0	0	0
T40	1689	0	0	0
T41	3272	0	0	0
T45	0	4	0	0
T65	0	4	0	0
T77	10054	0	0	0
T85	6668	0	0	0
T86	12252	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461201266	140	0	0
CgEnOn_A	461201266	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	140	0	0
T4	18821	0	0	0
T5	88951	0	0	0
T20	0	2	0	0
T35	52804	0	0	0
T38	1602	1	0	0
T39	7200	0	0	0
T40	1689	0	0	0
T41	3272	0	0	0
T45	0	4	0	0
T65	0	4	0	0
T77	10054	0	0	0
T85	6668	0	0	0
T86	12252	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	136	0	0
T4	18821	0	0	0
T5	88951	0	0	0
T20	0	2	0	0
T35	52804	0	0	0
T38	1602	1	0	0
T39	7200	0	0	0
T40	1689	0	0	0
T41	3272	0	0	0
T45	0	4	0	0
T65	0	4	0	0
T77	10054	0	0	0
T85	6668	0	0	0
T86	12252	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	3	0	0
T188	0	4	0	0
T189	0	3	0	0
T190	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Unreachable
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	221553224	138	0	0
CgEnOn_A	221553224	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553224	138	0	0
T4	9034	0	0	0
T5	42697	0	0	0
T20	0	3	0	0
T35	25346	0	0	0
T38	778	3	0	0
T39	3456	0	0	0
T40	810	0	0	0
T41	1570	0	0	0
T45	0	3	0	0
T65	0	4	0	0
T77	4826	0	0	0
T79	0	1	0	0
T85	3200	0	0	0
T86	5881	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	5	0	0
T188	0	6	0	0
T189	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553224	135	0	0
T4	9034	0	0	0
T5	42697	0	0	0
T20	0	3	0	0
T35	25346	0	0	0
T38	778	3	0	0
T39	3456	0	0	0
T40	810	0	0	0
T41	1570	0	0	0
T45	0	3	0	0
T65	0	4	0	0
T77	4826	0	0	0
T85	3200	0	0	0
T86	5881	0	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	5	0	0
T188	0	6	0	0
T189	0	2	0	0
T190	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T20,T45
1	0	Covered	T7,T8,T6
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107562629	8344	0	0
CgEnOn_A	107562629	5978	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	8344	0	0
T6	24443	1	0	0
T7	479	17	0	0
T8	1532	1	0	0
T26	659	1	0	0
T27	936	1	0	0
T28	287	1	0	0
T29	2425	1	0	0
T30	3825	1	0	0
T31	491	2	0	0
T32	2350	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107562629	5978	0	0
T2	0	191	0	0
T3	0	4	0	0
T6	24443	0	0	0
T7	479	16	0	0
T8	1532	0	0	0
T20	0	2	0	0
T25	0	56	0	0
T26	659	0	0	0
T27	936	0	0	0
T28	287	0	0	0
T29	2425	0	0	0
T30	3825	0	0	0
T31	491	1	0	0
T32	2350	0	0	0
T38	0	2	0	0
T87	0	18	0	0
T97	0	1	0	0
T99	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T20,T45
1	0	Covered	T7,T8,T6
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	215126538	8436	0	0
CgEnOn_A	215126538	6070	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126538	8436	0	0
T6	48886	1	0	0
T7	957	17	0	0
T8	3066	1	0	0
T26	1320	1	0	0
T27	1871	1	0	0
T28	573	1	0	0
T29	4852	1	0	0
T30	7650	1	0	0
T31	983	2	0	0
T32	4701	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215126538	6070	0	0
T2	0	201	0	0
T3	0	5	0	0
T6	48886	0	0	0
T7	957	16	0	0
T8	3066	0	0	0
T20	0	2	0	0
T25	0	55	0	0
T26	1320	0	0	0
T27	1871	0	0	0
T28	573	0	0	0
T29	4852	0	0	0
T30	7650	0	0	0
T31	983	1	0	0
T32	4701	0	0	0
T38	0	2	0	0
T87	0	20	0	0
T97	0	1	0	0
T99	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T20,T45
1	0	Covered	T7,T8,T6
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	431855825	8461	0	0
CgEnOn_A	431855825	6086	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431855825	8461	0	0
T6	97796	1	0	0
T7	1980	16	0	0
T8	5544	1	0	0
T26	2564	1	0	0
T27	3849	1	0	0
T28	1214	1	0	0
T29	8428	1	0	0
T30	15408	1	0	0
T31	2099	2	0	0
T32	8316	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431855825	6086	0	0
T2	0	192	0	0
T3	0	4	0	0
T6	97796	0	0	0
T7	1980	15	0	0
T8	5544	0	0	0
T20	0	2	0	0
T25	0	57	0	0
T26	2564	0	0	0
T27	3849	0	0	0
T28	1214	0	0	0
T29	8428	0	0	0
T30	15408	0	0	0
T31	2099	1	0	0
T32	8316	0	0	0
T38	0	2	0	0
T87	0	19	0	0
T97	0	1	0	0
T99	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T20,T45
1	0	Covered	T7,T8,T6
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	221553224	8389	0	0
CgEnOn_A	221553224	6014	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553224	8389	0	0
T6	54661	1	0	0
T7	989	16	0	0
T8	2772	1	0	0
T26	1282	1	0	0
T27	1925	1	0	0
T28	607	1	0	0
T29	4214	1	0	0
T30	7704	1	0	0
T31	1049	2	0	0
T32	4158	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221553224	6014	0	0
T2	0	190	0	0
T3	0	4	0	0
T6	54661	0	0	0
T7	989	15	0	0
T8	2772	0	0	0
T20	0	3	0	0
T25	0	60	0	0
T26	1282	0	0	0
T27	1925	0	0	0
T28	607	0	0	0
T29	4214	0	0	0
T30	7704	0	0	0
T31	1049	1	0	0
T32	4158	0	0	0
T38	0	3	0	0
T87	0	17	0	0
T97	0	1	0	0
T99	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Covered	T27,T30,T31
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461201266	4154	0	0
CgEnOn_A	461201266	4150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4154	0	0
T2	0	61	0	0
T3	0	8	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	21	0	0
T27	4010	10	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	3	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	11	0	0
T97	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4150	0	0
T2	0	61	0	0
T3	0	8	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	21	0	0
T27	4010	10	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	3	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	11	0	0
T97	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Covered	T27,T30,T31
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461201266	4011	0	0
CgEnOn_A	461201266	4007	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4011	0	0
T2	0	63	0	0
T3	0	10	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	20	0	0
T27	4010	7	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	1	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	10	0	0
T97	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4007	0	0
T2	0	63	0	0
T3	0	10	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	20	0	0
T27	4010	7	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	1	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	10	0	0
T97	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Covered	T27,T30,T31
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461201266	4171	0	0
CgEnOn_A	461201266	4167	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4171	0	0
T2	0	69	0	0
T3	0	10	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	23	0	0
T27	4010	8	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	2	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	10	0	0
T97	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4167	0	0
T2	0	69	0	0
T3	0	10	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	23	0	0
T27	4010	8	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	2	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	10	0	0
T97	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T4,T5
1	0	Covered	T27,T30,T31
1	1	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461201266	4141	0	0
CgEnOn_A	461201266	4137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4141	0	0
T2	0	60	0	0
T3	0	11	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	24	0	0
T27	4010	10	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	3	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	11	0	0
T97	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461201266	4137	0	0
T2	0	60	0	0
T3	0	11	0	0
T4	18821	0	0	0
T20	0	2	0	0
T25	0	24	0	0
T27	4010	10	0	0
T28	1265	0	0	0
T29	8780	0	0	0
T30	16050	3	0	0
T31	2186	1	0	0
T32	8662	0	0	0
T34	3935	0	0	0
T38	1602	1	0	0
T77	10054	0	0	0
T86	0	11	0	0
T97	0	1	0	0