Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	645592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3812692

1

T1

40

T2

128

T4

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1093415	1			T1	15		T2	23		T4	24
values[0x0]	1546562	1			T1	35		T2	104		T4	8
values[0x1]	1818307	1			T1	30		T2	129		T4	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	353081	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4105203

1

T1

49

T2

173

T4

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17417	1			T2	1		T3	6		T13	1
valid_sources[0x01]	17700	1			T2	1		T13	2		T5	5
valid_sources[0x02]	16953	1			T2	1		T3	3		T13	2
valid_sources[0x03]	17200	1			T2	3		T3	2		T6	3
valid_sources[0x04]	17293	1			T2	2		T13	3		T6	1
valid_sources[0x05]	17477	1			T3	3		T13	2		T6	1
valid_sources[0x06]	17177	1			T3	6		T13	1		T22	1
valid_sources[0x07]	17178	1			T2	1		T6	1		T7	173
valid_sources[0x08]	17285	1			T1	3		T2	1		T3	1
valid_sources[0x09]	18241	1			T2	1		T3	3		T5	1
valid_sources[0x0a]	16791	1			T2	3		T3	3		T23	1
valid_sources[0x0b]	18257	1			T2	2		T3	1		T17	1
valid_sources[0x0c]	17549	1			T2	2		T3	1		T13	1
valid_sources[0x0d]	18377	1			T13	1		T22	1		T6	4
valid_sources[0x0e]	17550	1			T1	4		T2	1		T3	2
valid_sources[0x0f]	18614	1			T1	10		T2	1		T3	3
valid_sources[0x10]	17066	1			T3	2		T13	1		T24	1
valid_sources[0x11]	17717	1			T2	4		T3	2		T13	1
valid_sources[0x12]	18447	1			T5	4		T127	1		T6	6
valid_sources[0x13]	17266	1			T1	1		T2	1		T3	2
valid_sources[0x14]	18347	1			T3	1		T13	1		T24	6
valid_sources[0x15]	17952	1			T1	1		T2	2		T3	2
valid_sources[0x16]	17067	1			T3	2		T13	2		T5	20
valid_sources[0x17]	16306	1			T1	1		T3	4		T13	1
valid_sources[0x18]	18764	1			T2	1		T13	1		T22	1
valid_sources[0x19]	16991	1			T13	1		T22	1		T6	4
valid_sources[0x1a]	17287	1			T1	1		T2	2		T3	1
valid_sources[0x1b]	18108	1			T24	6		T127	1		T6	3
valid_sources[0x1c]	17001	1			T3	3		T13	1		T24	1
valid_sources[0x1d]	17207	1			T2	2		T3	1		T13	2
valid_sources[0x1e]	16660	1			T1	1		T13	1		T6	2
valid_sources[0x1f]	17086	1			T2	2		T3	3		T13	4
valid_sources[0x20]	18018	1			T2	3		T3	1		T13	1
valid_sources[0x21]	16913	1			T2	1		T3	4		T13	2
valid_sources[0x22]	17348	1			T2	1		T3	1		T13	1
valid_sources[0x23]	16569	1			T3	4		T13	3		T22	3
valid_sources[0x24]	16876	1			T3	3		T13	1		T17	1
valid_sources[0x25]	17402	1			T2	1		T3	2		T13	1
valid_sources[0x26]	17850	1			T3	1		T5	1		T6	4
valid_sources[0x27]	20030	1			T2	1		T13	2		T24	9
valid_sources[0x28]	16728	1			T3	1		T13	1		T24	3
valid_sources[0x29]	17781	1			T2	1		T13	1		T22	1
valid_sources[0x2a]	16851	1			T3	1		T24	1		T6	5
valid_sources[0x2b]	17712	1			T3	5		T127	3		T6	3
valid_sources[0x2c]	16720	1			T3	2		T13	4		T22	1
valid_sources[0x2d]	17551	1			T3	1		T13	1		T22	1
valid_sources[0x2e]	16339	1			T2	1		T3	1		T13	1
valid_sources[0x2f]	16651	1			T2	2		T24	10		T6	3
valid_sources[0x30]	16781	1			T1	1		T3	3		T13	1
valid_sources[0x31]	17492	1			T2	3		T3	3		T13	1
valid_sources[0x32]	16229	1			T1	1		T3	4		T13	1
valid_sources[0x33]	16963	1			T3	3		T13	1		T22	1
valid_sources[0x34]	18297	1			T3	3		T13	1		T6	2
valid_sources[0x35]	18034	1			T1	2		T13	2		T6	3
valid_sources[0x36]	17198	1			T3	1		T13	1		T6	5
valid_sources[0x37]	17747	1			T13	2		T22	2		T24	6
valid_sources[0x38]	18599	1			T13	1		T6	2		T37	1
valid_sources[0x39]	17583	1			T3	3		T13	2		T6	2
valid_sources[0x3a]	18180	1			T2	2		T127	2		T6	2
valid_sources[0x3b]	17150	1			T2	2		T3	2		T13	1
valid_sources[0x3c]	17853	1			T2	1		T3	5		T13	2
valid_sources[0x3d]	17164	1			T2	2		T3	10		T6	6
valid_sources[0x3e]	17422	1			T4	7		T12	10		T3	2
valid_sources[0x3f]	17822	1			T1	2		T2	1		T3	6
valid_sources[0x40]	17562	1			T3	6		T13	1		T6	9
valid_sources[0x41]	17995	1			T3	2		T127	1		T6	5
valid_sources[0x42]	17873	1			T2	1		T3	3		T13	3
valid_sources[0x43]	17101	1			T1	2		T3	6		T37	2
valid_sources[0x44]	16571	1			T3	1		T6	8		T101	1
valid_sources[0x45]	17969	1			T1	3		T3	2		T36	2
valid_sources[0x46]	17259	1			T3	1		T23	1		T6	7
valid_sources[0x47]	17734	1			T3	2		T13	1		T5	1
valid_sources[0x48]	17407	1			T2	1		T13	1		T14	1
valid_sources[0x49]	16730	1			T2	1		T3	2		T13	1
valid_sources[0x4a]	17323	1			T2	2		T3	3		T14	1
valid_sources[0x4b]	19016	1			T2	1		T3	2		T13	2
valid_sources[0x4c]	18692	1			T2	2		T3	1		T13	2
valid_sources[0x4d]	17551	1			T1	1		T2	2		T3	4
valid_sources[0x4e]	16954	1			T2	1		T3	5		T22	1
valid_sources[0x4f]	17880	1			T1	2		T2	1		T3	3
valid_sources[0x50]	16518	1			T1	1		T2	1		T13	1
valid_sources[0x51]	17073	1			T2	2		T3	2		T13	1
valid_sources[0x52]	16079	1			T1	4		T3	1		T14	1
valid_sources[0x53]	17283	1			T3	6		T13	3		T24	3
valid_sources[0x54]	17644	1			T13	3		T24	10		T6	6
valid_sources[0x55]	17153	1			T2	2		T3	2		T13	1
valid_sources[0x56]	17152	1			T2	2		T3	3		T22	1
valid_sources[0x57]	17881	1			T13	2		T127	2		T6	4
valid_sources[0x58]	17384	1			T2	1		T13	2		T14	1
valid_sources[0x59]	17767	1			T3	1		T6	1		T7	196
valid_sources[0x5a]	17897	1			T2	2		T3	3		T13	1
valid_sources[0x5b]	17058	1			T3	1		T6	2		T7	198
valid_sources[0x5c]	16634	1			T3	4		T24	9		T127	1
valid_sources[0x5d]	16140	1			T2	1		T3	3		T13	1
valid_sources[0x5e]	18479	1			T2	1		T3	2		T24	1
valid_sources[0x5f]	17559	1			T2	1		T13	2		T127	2
valid_sources[0x60]	17486	1			T2	2		T3	3		T13	2
valid_sources[0x61]	17721	1			T3	2		T13	2		T5	2
valid_sources[0x62]	15882	1			T13	3		T6	5		T7	192
valid_sources[0x63]	17580	1			T2	3		T3	4		T13	1
valid_sources[0x64]	17840	1			T2	1		T13	2		T14	1
valid_sources[0x65]	17465	1			T2	1		T3	1		T125	2
valid_sources[0x66]	18788	1			T3	1		T13	1		T23	2
valid_sources[0x67]	17302	1			T3	2		T96	1		T101	1
valid_sources[0x68]	17973	1			T1	2		T2	1		T13	1
valid_sources[0x69]	16715	1			T1	1		T2	1		T3	2
valid_sources[0x6a]	17314	1			T2	3		T14	1		T6	6
valid_sources[0x6b]	16766	1			T2	1		T3	1		T13	2
valid_sources[0x6c]	16904	1			T3	5		T13	3		T24	2
valid_sources[0x6d]	18224	1			T3	2		T13	1		T35	4
valid_sources[0x6e]	17323	1			T13	1		T22	1		T6	3
valid_sources[0x6f]	16949	1			T3	1		T13	1		T6	5
valid_sources[0x70]	17251	1			T2	1		T4	14		T13	3
valid_sources[0x71]	17019	1			T2	1		T3	1		T13	2
valid_sources[0x72]	18092	1			T2	1		T3	3		T14	1
valid_sources[0x73]	16540	1			T2	2		T3	2		T13	1
valid_sources[0x74]	16190	1			T1	1		T13	1		T22	2
valid_sources[0x75]	17731	1			T1	1		T22	1		T5	3
valid_sources[0x76]	17381	1			T3	3		T5	9		T6	4
valid_sources[0x77]	17404	1			T2	1		T3	3		T22	1
valid_sources[0x78]	16855	1			T2	2		T3	3		T22	1
valid_sources[0x79]	17574	1			T2	3		T3	1		T22	2
valid_sources[0x7a]	16877	1			T2	3		T23	1		T5	13
valid_sources[0x7b]	16540	1			T2	2		T3	1		T13	1
valid_sources[0x7c]	17685	1			T2	5		T3	2		T14	1
valid_sources[0x7d]	18685	1			T13	1		T22	1		T6	1
valid_sources[0x7e]	17023	1			T3	2		T13	1		T127	1
valid_sources[0x7f]	18685	1			T24	4		T35	16		T6	6
valid_sources[0x80]	16630	1			T2	1		T13	2		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

961676

1

T1

6

T2

12

T4

11

values[0x0]

all_enables

biggest_size

1450000

1

T1

21

T2

70

T4

6

values[0x1]

all_enables

biggest_size

1401016

1

T1

13

T2

46

T4

2