Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T36,T6
0	1	Covered	T14,T6,T100
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T36,T6
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	897508630	13869	0	0
GateOpen_A	897508630	20937	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	897508630	13869	0	0
T5	306950	0	0	0
T6	0	22	0	0
T7	0	206	0	0
T14	5130	22	0	0
T15	9227	0	0	0
T16	3050	0	0	0
T17	12657	0	0	0
T18	132267	0	0	0
T22	6259	0	0	0
T23	34936	0	0	0
T24	345662	0	0	0
T32	0	19	0	0
T33	0	23	0	0
T34	0	16	0	0
T36	0	2	0	0
T37	0	4	0	0
T79	0	29	0	0
T82	0	2	0	0
T84	5280	0	0	0
T100	0	13	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	897508630	20937	0	0
T1	69598	4	0	0
T2	288422	0	0	0
T3	535723	0	0	0
T4	15244	4	0	0
T12	5070	0	0	0
T13	244246	4	0	0
T14	5130	26	0	0
T15	9227	4	0	0
T16	3050	4	0	0
T17	12657	0	0	0
T18	0	4	0	0
T22	0	4	0	0
T23	0	4	0	0
T84	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T6,T32
0	1	Covered	T14,T6,T100
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T37
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	98820618	3265	0	0
GateOpen_A	98820618	5031	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820618	3265	0	0
T5	34088	0	0	0
T6	0	4	0	0
T7	0	49	0	0
T14	541	4	0	0
T15	1083	0	0	0
T16	337	0	0	0
T17	1389	0	0	0
T18	14683	0	0	0
T22	689	0	0	0
T23	4296	0	0	0
T24	36483	0	0	0
T32	0	5	0	0
T33	0	6	0	0
T34	0	4	0	0
T37	0	1	0	0
T79	0	9	0	0
T82	0	1	0	0
T84	583	0	0	0
T100	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820618	5031	0	0
T1	7722	1	0	0
T2	32027	0	0	0
T3	59518	0	0	0
T4	1674	1	0	0
T12	576	0	0	0
T13	26483	1	0	0
T14	541	5	0	0
T15	1083	1	0	0
T16	337	1	0	0
T17	1389	0	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T84	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T36,T6
0	1	Covered	T14,T6,T100
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T36,T6
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	197642094	3530	0	0
GateOpen_A	197642094	5296	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197642094	3530	0	0
T5	68175	0	0	0
T6	0	5	0	0
T7	0	54	0	0
T14	1082	6	0	0
T15	2168	0	0	0
T16	673	0	0	0
T17	2777	0	0	0
T18	29366	0	0	0
T22	1378	0	0	0
T23	8597	0	0	0
T24	72965	0	0	0
T32	0	5	0	0
T33	0	6	0	0
T34	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T79	0	7	0	0
T84	1165	0	0	0
T100	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197642094	5296	0	0
T1	15444	1	0	0
T2	64053	0	0	0
T3	119036	0	0	0
T4	3347	1	0	0
T12	1152	0	0	0
T13	52965	1	0	0
T14	1082	7	0	0
T15	2168	1	0	0
T16	673	1	0	0
T17	2777	0	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T84	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T36,T6
0	1	Covered	T14,T6,T100
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T36,T6
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	396933385	3540	0	0
GateOpen_A	396933385	5308	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396933385	3540	0	0
T5	136456	0	0	0
T6	0	6	0	0
T7	0	52	0	0
T14	2338	5	0	0
T15	3984	0	0	0
T16	1360	0	0	0
T17	5660	0	0	0
T18	58811	0	0	0
T22	2795	0	0	0
T23	14695	0	0	0
T24	145953	0	0	0
T32	0	5	0	0
T33	0	6	0	0
T34	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T79	0	7	0	0
T84	2355	0	0	0
T100	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396933385	5308	0	0
T1	30954	1	0	0
T2	128226	0	0	0
T3	238109	0	0	0
T4	6815	1	0	0
T12	2228	0	0	0
T13	106023	1	0	0
T14	2338	6	0	0
T15	3984	1	0	0
T16	1360	1	0	0
T17	5660	0	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T84	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T6,T32
0	1	Covered	T14,T6,T100
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T37
1	0	Covered	T32,T33,T34
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	204112533	3534	0	0
GateOpen_A	204112533	5302	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204112533	3534	0	0
T5	68231	0	0	0
T6	0	7	0	0
T7	0	51	0	0
T14	1169	7	0	0
T15	1992	0	0	0
T16	680	0	0	0
T17	2831	0	0	0
T18	29407	0	0	0
T22	1397	0	0	0
T23	7348	0	0	0
T24	90261	0	0	0
T32	0	4	0	0
T33	0	5	0	0
T34	0	4	0	0
T37	0	1	0	0
T79	0	6	0	0
T82	0	1	0	0
T84	1177	0	0	0
T100	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204112533	5302	0	0
T1	15478	1	0	0
T2	64116	0	0	0
T3	119060	0	0	0
T4	3408	1	0	0
T12	1114	0	0	0
T13	58775	1	0	0
T14	1169	8	0	0
T15	1992	1	0	0
T16	680	1	0	0
T17	2831	0	0	0
T18	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T84	0	1	0	0