Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	809241500	75970	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	809241500	75970	0	0
T1	154765	110	0	0
T2	160280	39	0	0
T3	1203015	563	0	0
T4	8515	0	0	0
T5	0	49	0	0
T6	0	127	0	0
T7	0	546	0	0
T8	0	173	0	0
T9	0	151	0	0
T10	0	621	0	0
T11	0	2456	0	0
T12	6500	0	0	0
T13	228670	0	0	0
T14	12175	0	0	0
T15	9750	0	0	0
T16	6870	0	0	0
T17	7070	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161848300	11242	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	11242	0	0
T1	30953	16	0	0
T2	32056	6	0	0
T3	240603	75	0	0
T4	1703	0	0	0
T5	0	8	0	0
T6	0	21	0	0
T7	0	88	0	0
T8	0	27	0	0
T9	0	28	0	0
T10	0	92	0	0
T11	0	358	0	0
T12	1300	0	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	0	0	0
T16	1374	0	0	0
T17	1414	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161848300	10837	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	10837	0	0
T1	30953	14	0	0
T2	32056	6	0	0
T3	240603	74	0	0
T4	1703	0	0	0
T5	0	8	0	0
T6	0	21	0	0
T7	0	86	0	0
T8	0	27	0	0
T9	0	28	0	0
T10	0	78	0	0
T11	0	306	0	0
T12	1300	0	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	0	0	0
T16	1374	0	0	0
T17	1414	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161848300	15168	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	15168	0	0
T1	30953	22	0	0
T2	32056	8	0	0
T3	240603	112	0	0
T4	1703	0	0	0
T5	0	10	0	0
T6	0	26	0	0
T7	0	110	0	0
T8	0	35	0	0
T9	0	29	0	0
T10	0	124	0	0
T11	0	484	0	0
T12	1300	0	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	0	0	0
T16	1374	0	0	0
T17	1414	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161848300	15238	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	15238	0	0
T1	30953	22	0	0
T2	32056	8	0	0
T3	240603	113	0	0
T4	1703	0	0	0
T5	0	10	0	0
T6	0	26	0	0
T7	0	110	0	0
T8	0	35	0	0
T9	0	29	0	0
T10	0	126	0	0
T11	0	488	0	0
T12	1300	0	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	0	0	0
T16	1374	0	0	0
T17	1414	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	161848300	23485	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	23485	0	0
T1	30953	36	0	0
T2	32056	11	0	0
T3	240603	189	0	0
T4	1703	0	0	0
T5	0	13	0	0
T6	0	33	0	0
T7	0	152	0	0
T8	0	49	0	0
T9	0	37	0	0
T10	0	201	0	0
T11	0	820	0	0
T12	1300	0	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	0	0	0
T16	1374	0	0	0
T17	1414	0	0	0