Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Unreachable
1	0	Covered	T14,T6,T7

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	161848300	159096547	0	0
AllClkBypReqTrue_A	161848300	127238	0	0
IoClkBypReqFalse_A	161848300	159015795	0	2415
IoClkBypReqTrue_A	161848300	203142	0	0
LcClkBypAckFalse_A	161848300	159105438	0	0
LcClkBypAckTrue_A	161848300	118347	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	159096547	0	0
T1	30953	30790	0	0
T2	32056	32001	0	0
T3	240603	240522	0	0
T4	1703	1658	0	0
T12	1300	1166	0	0
T13	45734	45683	0	0
T14	2435	1992	0	0
T15	1950	1713	0	0
T16	1374	1168	0	0
T17	1414	1373	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	127238	0	0
T3	240603	0	0	0
T6	0	251	0	0
T12	1300	70	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	150	0	0
T16	1374	0	0	0
T17	1414	0	0	0
T22	2794	0	0	0
T23	1990	245	0	0
T24	188224	0	0	0
T35	0	112	0	0
T84	0	32	0	0
T96	0	206	0	0
T97	0	115	0	0
T118	0	46	0	0
T124	0	212	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	159015795	0	2415
T1	30953	30788	0	3
T2	32056	31999	0	3
T3	240603	240520	0	3
T4	1703	1656	0	3
T12	1300	1121	0	3
T13	45734	45681	0	3
T14	2435	1988	0	3
T15	1950	1556	0	3
T16	1374	1091	0	3
T17	1414	1371	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	203142	0	0
T3	240603	0	0	0
T6	0	479	0	0
T12	1300	113	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	305	0	0
T16	1374	75	0	0
T17	1414	0	0	0
T22	2794	0	0	0
T23	1990	408	0	0
T24	188224	0	0	0
T84	0	31	0	0
T96	0	246	0	0
T118	0	200	0	0
T124	0	267	0	0
T125	0	376	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	159105438	0	0
T1	30953	30790	0	0
T2	32056	32001	0	0
T3	240603	240522	0	0
T4	1703	1658	0	0
T12	1300	1182	0	0
T13	45734	45683	0	0
T14	2435	1992	0	0
T15	1950	1666	0	0
T16	1374	1104	0	0
T17	1414	1373	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	118347	0	0
T3	240603	0	0	0
T6	0	233	0	0
T12	1300	54	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	197	0	0
T16	1374	64	0	0
T17	1414	0	0	0
T22	2794	0	0	0
T23	1990	231	0	0
T24	188224	0	0	0
T96	0	134	0	0
T118	0	81	0	0
T124	0	172	0	0
T125	0	138	0	0
T126	0	30	0	0