Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1702130736	15659	0	0
TransStop_A	1702130736	7942	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702130736	15659	0	0
T3	992152	0	0	0
T4	28396	13	0	0
T6	0	7	0	0
T12	9284	0	0	0
T13	609780	0	0	0
T14	9744	0	0	0
T15	16604	0	0	0
T16	5664	0	0	0
T17	23584	9	0	0
T22	11648	32	0	0
T23	61232	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T98	0	35	0	0
T99	0	20	0	0
T101	0	23	0	0
T127	0	37	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702130736	7942	0	0
T3	496076	0	0	0
T4	14198	2	0	0
T5	284292	0	0	0
T6	0	6	0	0
T7	0	31	0	0
T12	4642	0	0	0
T13	304890	0	0	0
T14	4872	0	0	0
T15	8302	0	0	0
T16	2832	0	0	0
T17	23584	9	0	0
T18	122526	0	0	0
T22	11648	7	0	0
T23	61232	0	0	0
T24	328080	0	0	0
T35	4456	0	0	0
T36	3380	4	0	0
T37	0	4	0	0
T84	4906	0	0	0
T98	0	16	0	0
T99	0	6	0	0
T101	0	12	0	0
T127	14254	30	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	425532684	3938	0	0
TransStop_A	425532684	1985	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	3938	0	0
T3	248038	0	0	0
T4	7099	4	0	0
T6	0	1	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2436	0	0	0
T15	4151	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2912	13	0	0
T23	15308	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	6	0	0
T99	0	4	0	0
T101	0	5	0	0
T127	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	1985	0	0
T5	142146	0	0	0
T6	0	1	0	0
T7	0	15	0	0
T17	5896	2	0	0
T18	61263	0	0	0
T22	2912	3	0	0
T23	15308	0	0	0
T24	164040	0	0	0
T35	2228	0	0	0
T36	1690	1	0	0
T37	0	1	0	0
T84	2453	0	0	0
T98	0	2	0	0
T99	0	2	0	0
T101	0	3	0	0
T127	7127	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	425532684	3910	0	0
TransStop_A	425532684	1980	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	3910	0	0
T3	248038	0	0	0
T4	7099	3	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2436	0	0	0
T15	4151	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2912	5	0	0
T23	15308	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	10	0	0
T99	0	5	0	0
T101	0	6	0	0
T127	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	1980	0	0
T5	142146	0	0	0
T6	0	2	0	0
T7	0	16	0	0
T17	5896	2	0	0
T18	61263	0	0	0
T22	2912	1	0	0
T23	15308	0	0	0
T24	164040	0	0	0
T35	2228	0	0	0
T36	1690	1	0	0
T37	0	1	0	0
T84	2453	0	0	0
T98	0	4	0	0
T99	0	1	0	0
T101	0	2	0	0
T127	7127	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	425532684	3915	0	0
TransStop_A	425532684	2003	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	3915	0	0
T3	248038	0	0	0
T4	7099	4	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2436	0	0	0
T15	4151	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2912	8	0	0
T23	15308	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	9	0	0
T99	0	6	0	0
T101	0	7	0	0
T127	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	2003	0	0
T3	248038	0	0	0
T4	7099	1	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2436	0	0	0
T15	4151	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2912	1	0	0
T23	15308	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	4	0	0
T99	0	1	0	0
T101	0	4	0	0
T127	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	425532684	3896	0	0
TransStop_A	425532684	1974	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	3896	0	0
T3	248038	0	0	0
T4	7099	2	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2436	0	0	0
T15	4151	0	0	0
T16	1416	0	0	0
T17	5896	3	0	0
T22	2912	6	0	0
T23	15308	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	10	0	0
T99	0	5	0	0
T101	0	5	0	0
T127	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532684	1974	0	0
T3	248038	0	0	0
T4	7099	1	0	0
T6	0	1	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2436	0	0	0
T15	4151	0	0	0
T16	1416	0	0	0
T17	5896	3	0	0
T22	2912	2	0	0
T23	15308	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	6	0	0
T99	0	2	0	0
T101	0	3	0	0
T127	0	8	0	0