Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	162839091	5581896	0	0
clk_enables_rd_A	162839091	32557	0	0
clk_hints_rd_A	162839091	29488	0	0
extclk_ctrl_rd_A	162839091	36467	0	0
extclk_ctrl_regwen_rd_A	162839091	28304	0	0
jitter_enable_rd_A	162839091	39946	0	0
jitter_regwen_rd_A	162839091	31842	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162839091	5581896	0	0
T7	217151	63976	0	0
T8	112156	0	0	0
T9	27415	0	0	0
T11	0	183038	0	0
T25	0	177754	0	0
T70	0	159861	0	0
T71	0	132609	0	0
T72	0	123401	0	0
T73	0	132208	0	0
T74	0	94370	0	0
T75	0	78246	0	0
T76	0	51478	0	0
T77	2068	0	0	0
T78	1720	0	0	0
T79	805	0	0	0
T80	2283	0	0	0
T81	2104	0	0	0
T82	2216	0	0	0
T83	2801	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162839091	32557	0	0
T7	217151	2415	0	0
T8	112156	0	0	0
T9	27415	0	0	0
T71	0	5185	0	0
T76	0	2158	0	0
T77	2068	0	0	0
T78	1720	0	0	0
T79	805	0	0	0
T80	2283	0	0	0
T81	2104	0	0	0
T82	2216	3	0	0
T83	2801	0	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	1	0	0
T153	0	1671	0	0
T154	0	10	0	0
T155	0	3215	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162839091	29488	0	0
T7	217151	2122	0	0
T8	112156	0	0	0
T9	27415	0	0	0
T71	0	4384	0	0
T76	0	1795	0	0
T77	2068	0	0	0
T78	1720	0	0	0
T79	805	0	0	0
T80	2283	0	0	0
T81	2104	0	0	0
T82	2216	3	0	0
T83	2801	0	0	0
T151	0	2	0	0
T153	0	1528	0	0
T154	0	5	0	0
T155	0	3013	0	0
T156	0	4	0	0
T157	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162839091	36467	0	0
T3	240603	0	0	0
T7	0	2528	0	0
T12	1300	10	0	0
T13	45734	0	0	0
T14	2435	0	0	0
T15	1950	22	0	0
T16	1374	0	0	0
T17	1414	0	0	0
T19	0	42	0	0
T22	2794	0	0	0
T23	1990	0	0	0
T24	188224	0	0	0
T35	0	35	0	0
T57	0	5	0	0
T71	0	5433	0	0
T81	0	64	0	0
T114	0	91	0	0
T158	0	50	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162839091	28304	0	0
T7	217151	2069	0	0
T8	112156	0	0	0
T9	27415	0	0	0
T57	0	1	0	0
T71	0	4523	0	0
T76	0	1697	0	0
T77	2068	0	0	0
T78	1720	0	0	0
T79	805	0	0	0
T80	2283	0	0	0
T81	2104	0	0	0
T82	2216	0	0	0
T83	2801	0	0	0
T114	0	53	0	0
T153	0	1491	0	0
T159	0	17	0	0
T160	0	17	0	0
T161	0	7	0	0
T162	0	53	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162839091	39946	0	0
T7	217151	2639	0	0
T8	112156	0	0	0
T9	27415	0	0	0
T71	0	5531	0	0
T76	0	2647	0	0
T77	2068	0	0	0
T78	1720	0	0	0
T79	805	0	0	0
T80	2283	0	0	0
T81	2104	0	0	0
T82	2216	100	0	0
T83	2801	0	0	0
T150	0	58	0	0
T151	0	122	0	0
T152	0	109	0	0
T153	0	2209	0	0
T156	0	123	0	0
T157	0	116	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162839091	31842	0	0
T7	217151	2325	0	0
T8	112156	0	0	0
T9	27415	0	0	0
T71	0	5146	0	0
T76	0	2118	0	0
T77	2068	0	0	0
T78	1720	0	0	0
T79	805	0	0	0
T80	2283	0	0	0
T81	2104	0	0	0
T82	2216	0	0	0
T83	2801	0	0	0
T153	0	1789	0	0
T155	0	3581	0	0
T163	0	1079	0	0
T164	0	2322	0	0
T165	0	549	0	0
T166	0	2395	0	0
T167	0	1906	0	0