Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	485544900	479	0	0
StatusRise_A	485544900	479	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485544900	479	0	0
T32	3174	14	0	0
T33	3159	16	0	0
T34	3747	12	0	0
T37	3711	0	0	0
T40	0	5	0	0
T55	0	13	0	0
T99	8388	0	0	0
T100	2172	0	0	0
T101	8796	0	0	0
T118	4707	0	0	0
T124	4659	0	0	0
T126	3894	0	0	0
T168	0	10	0	0
T169	0	4	0	0
T170	0	14	0	0
T171	0	8	0	0
T172	0	8	0	0
T173	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485544900	479	0	0
T32	3174	14	0	0
T33	3159	16	0	0
T34	3747	12	0	0
T37	3711	0	0	0
T40	0	5	0	0
T55	0	13	0	0
T99	8388	0	0	0
T100	2172	0	0	0
T101	8796	0	0	0
T118	4707	0	0	0
T124	4659	0	0	0
T126	3894	0	0	0
T168	0	10	0	0
T169	0	4	0	0
T170	0	14	0	0
T171	0	8	0	0
T172	0	8	0	0
T173	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161848300	163	0	0
StatusRise_A	161848300	163	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	163	0	0
T32	1058	5	0	0
T33	1053	5	0	0
T34	1249	4	0	0
T37	1237	0	0	0
T55	0	5	0	0
T99	2796	0	0	0
T100	724	0	0	0
T101	2932	0	0	0
T118	1569	0	0	0
T124	1553	0	0	0
T126	1298	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	163	0	0
T32	1058	5	0	0
T33	1053	5	0	0
T34	1249	4	0	0
T37	1237	0	0	0
T55	0	5	0	0
T99	2796	0	0	0
T100	724	0	0	0
T101	2932	0	0	0
T118	1569	0	0	0
T124	1553	0	0	0
T126	1298	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161848300	162	0	0
StatusRise_A	161848300	162	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	162	0	0
T32	1058	5	0	0
T33	1053	6	0	0
T34	1249	4	0	0
T37	1237	0	0	0
T40	0	5	0	0
T55	0	5	0	0
T99	2796	0	0	0
T100	724	0	0	0
T101	2932	0	0	0
T118	1569	0	0	0
T124	1553	0	0	0
T126	1298	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0
T173	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	162	0	0
T32	1058	5	0	0
T33	1053	6	0	0
T34	1249	4	0	0
T37	1237	0	0	0
T40	0	5	0	0
T55	0	5	0	0
T99	2796	0	0	0
T100	724	0	0	0
T101	2932	0	0	0
T118	1569	0	0	0
T124	1553	0	0	0
T126	1298	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0
T173	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	161848300	154	0	0
StatusRise_A	161848300	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	154	0	0
T32	1058	4	0	0
T33	1053	5	0	0
T34	1249	4	0	0
T37	1237	0	0	0
T55	0	3	0	0
T99	2796	0	0	0
T100	724	0	0	0
T101	2932	0	0	0
T118	1569	0	0	0
T124	1553	0	0	0
T126	1298	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	3	0	0
T173	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161848300	154	0	0
T32	1058	4	0	0
T33	1053	5	0	0
T34	1249	4	0	0
T37	1237	0	0	0
T55	0	3	0	0
T99	2796	0	0	0
T100	724	0	0	0
T101	2932	0	0	0
T118	1569	0	0	0
T124	1553	0	0	0
T126	1298	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	3	0	0
T173	0	1	0	0