Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49371	0	0
CgEnOn_A	2147483647	39656	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49371	0	0
T1	54119	3	0	0
T2	224303	3	0	0
T3	664700	3	0	0
T4	18933	7	0	0
T11	0	5	0	0
T12	6275	3	0	0
T13	337914	3	0	0
T14	6394	33	0	0
T15	11384	3	0	0
T16	3784	3	0	0
T17	15721	5	0	0
T22	2911	13	0	0
T32	8629	30	0	0
T33	8018	35	0	0
T34	4772	20	0	0
T37	5497	0	0	0
T55	0	25	0	0
T74	0	5	0	0
T99	5950	0	0	0
T100	7785	0	0	0
T101	6200	0	0	0
T118	7200	0	0	0
T124	30586	0	0	0
T126	11770	0	0	0
T168	0	20	0	0
T170	0	20	0	0
T171	0	10	0	0
T172	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39656	0	0
T4	7099	4	0	0
T5	238716	0	0	0
T6	0	30	0	0
T7	0	257	0	0
T11	0	5	0	0
T14	6394	27	0	0
T15	11384	0	0	0
T16	3784	0	0	0
T17	15721	2	0	0
T18	102858	0	0	0
T22	7772	0	0	0
T23	42896	0	0	0
T24	255399	0	0	0
T32	8629	45	0	0
T33	8018	53	0	0
T34	4772	32	0	0
T36	0	3	0	0
T37	5497	4	0	0
T55	0	25	0	0
T74	0	4	0	0
T79	0	34	0	0
T82	0	1	0	0
T84	4101	0	0	0
T99	5950	0	0	0
T100	7785	26	0	0
T101	6200	0	0	0
T118	7200	0	0	0
T124	30586	0	0	0
T126	11770	0	0	0
T168	0	20	0	0
T170	0	20	0	0
T171	0	10	0	0
T172	0	15	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	197641692	168	0	0
CgEnOn_A	197641692	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197641692	168	0	0
T11	0	1	0	0
T32	1894	5	0	0
T33	1752	6	0	0
T34	1040	4	0	0
T37	1210	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	1295	0	0	0
T100	1721	0	0	0
T101	1354	0	0	0
T118	1625	0	0	0
T124	7267	0	0	0
T126	2630	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197641692	168	0	0
T11	0	1	0	0
T32	1894	5	0	0
T33	1752	6	0	0
T34	1040	4	0	0
T37	1210	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	1295	0	0	0
T100	1721	0	0	0
T101	1354	0	0	0
T118	1625	0	0	0
T124	7267	0	0	0
T126	2630	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98820198	168	0	0
CgEnOn_A	98820198	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	168	0	0
T11	0	1	0	0
T32	947	5	0	0
T33	876	6	0	0
T34	520	4	0	0
T37	605	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	648	0	0	0
T100	861	0	0	0
T101	677	0	0	0
T118	813	0	0	0
T124	3632	0	0	0
T126	1315	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	168	0	0
T11	0	1	0	0
T32	947	5	0	0
T33	876	6	0	0
T34	520	4	0	0
T37	605	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	648	0	0	0
T100	861	0	0	0
T101	677	0	0	0
T118	813	0	0	0
T124	3632	0	0	0
T126	1315	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98820198	168	0	0
CgEnOn_A	98820198	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	168	0	0
T11	0	1	0	0
T32	947	5	0	0
T33	876	6	0	0
T34	520	4	0	0
T37	605	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	648	0	0	0
T100	861	0	0	0
T101	677	0	0	0
T118	813	0	0	0
T124	3632	0	0	0
T126	1315	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	168	0	0
T11	0	1	0	0
T32	947	5	0	0
T33	876	6	0	0
T34	520	4	0	0
T37	605	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	648	0	0	0
T100	861	0	0	0
T101	677	0	0	0
T118	813	0	0	0
T124	3632	0	0	0
T126	1315	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98820198	168	0	0
CgEnOn_A	98820198	168	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	168	0	0
T11	0	1	0	0
T32	947	5	0	0
T33	876	6	0	0
T34	520	4	0	0
T37	605	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	648	0	0	0
T100	861	0	0	0
T101	677	0	0	0
T118	813	0	0	0
T124	3632	0	0	0
T126	1315	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	168	0	0
T11	0	1	0	0
T32	947	5	0	0
T33	876	6	0	0
T34	520	4	0	0
T37	605	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	648	0	0	0
T100	861	0	0	0
T101	677	0	0	0
T118	813	0	0	0
T124	3632	0	0	0
T126	1315	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396932931	168	0	0
CgEnOn_A	396932931	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396932931	168	0	0
T11	0	1	0	0
T32	3894	5	0	0
T33	3638	6	0	0
T34	2172	4	0	0
T37	2472	0	0	0
T55	0	5	0	0
T74	0	1	0	0
T99	2711	0	0	0
T100	3481	0	0	0
T101	2815	0	0	0
T118	3136	0	0	0
T124	12423	0	0	0
T126	5195	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396932931	166	0	0
T11	0	1	0	0
T32	3894	5	0	0
T33	3638	6	0	0
T34	2172	4	0	0
T37	2472	0	0	0
T55	0	5	0	0
T99	2711	0	0	0
T100	3481	0	0	0
T101	2815	0	0	0
T118	3136	0	0	0
T124	12423	0	0	0
T126	5195	0	0	0
T168	0	4	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	3	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	425532238	168	0	0
CgEnOn_A	425532238	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	168	0	0
T7	0	1	0	0
T32	3965	5	0	0
T33	3829	5	0	0
T34	2228	4	0	0
T37	2576	0	0	0
T55	0	5	0	0
T71	0	1	0	0
T99	2824	0	0	0
T100	3626	0	0	0
T101	2932	0	0	0
T118	3268	0	0	0
T124	12941	0	0	0
T126	5412	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	163	0	0
T32	3965	5	0	0
T33	3829	5	0	0
T34	2228	4	0	0
T37	2576	0	0	0
T55	0	5	0	0
T99	2824	0	0	0
T100	3626	0	0	0
T101	2932	0	0	0
T118	3268	0	0	0
T124	12941	0	0	0
T126	5412	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	425532238	168	0	0
CgEnOn_A	425532238	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	168	0	0
T7	0	1	0	0
T32	3965	5	0	0
T33	3829	5	0	0
T34	2228	4	0	0
T37	2576	0	0	0
T55	0	5	0	0
T71	0	1	0	0
T99	2824	0	0	0
T100	3626	0	0	0
T101	2932	0	0	0
T118	3268	0	0	0
T124	12941	0	0	0
T126	5412	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	163	0	0
T32	3965	5	0	0
T33	3829	5	0	0
T34	2228	4	0	0
T37	2576	0	0	0
T55	0	5	0	0
T99	2824	0	0	0
T100	3626	0	0	0
T101	2932	0	0	0
T118	3268	0	0	0
T124	12941	0	0	0
T126	5412	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	4	0	0
T172	0	2	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Unreachable
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204112110	157	0	0
CgEnOn_A	204112110	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204112110	157	0	0
T32	1885	4	0	0
T33	1665	5	0	0
T34	1154	4	0	0
T37	1237	0	0	0
T55	0	3	0	0
T99	1355	0	0	0
T100	1740	0	0	0
T101	1407	0	0	0
T118	1569	0	0	0
T124	6211	0	0	0
T126	2597	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	3	0	0
T173	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204112110	154	0	0
T32	1885	4	0	0
T33	1665	5	0	0
T34	1154	4	0	0
T37	1237	0	0	0
T55	0	3	0	0
T99	1355	0	0	0
T100	1740	0	0	0
T101	1407	0	0	0
T118	1569	0	0	0
T124	6211	0	0	0
T126	2597	0	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	5	0	0
T171	0	2	0	0
T172	0	3	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98820198	7861	0	0
CgEnOn_A	98820198	5443	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	7861	0	0
T1	7722	1	0	0
T2	32026	1	0	0
T3	59518	1	0	0
T4	1673	1	0	0
T12	575	1	0	0
T13	26482	1	0	0
T14	540	11	0	0
T15	1083	1	0	0
T16	336	1	0	0
T17	1388	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98820198	5443	0	0
T5	34087	0	0	0
T6	0	9	0	0
T7	0	83	0	0
T14	540	9	0	0
T15	1083	0	0	0
T16	336	0	0	0
T17	1388	0	0	0
T18	14683	0	0	0
T22	689	0	0	0
T23	4296	0	0	0
T24	36482	0	0	0
T32	0	5	0	0
T33	0	6	0	0
T34	0	4	0	0
T37	0	1	0	0
T79	0	12	0	0
T82	0	1	0	0
T84	582	0	0	0
T100	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	197641692	7936	0	0
CgEnOn_A	197641692	5518	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197641692	7936	0	0
T1	15444	1	0	0
T2	64052	1	0	0
T3	119035	1	0	0
T4	3347	1	0	0
T12	1152	1	0	0
T13	52965	1	0	0
T14	1082	12	0	0
T15	2167	1	0	0
T16	673	1	0	0
T17	2777	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197641692	5518	0	0
T5	68174	0	0	0
T6	0	10	0	0
T7	0	86	0	0
T14	1082	10	0	0
T15	2167	0	0	0
T16	673	0	0	0
T17	2777	0	0	0
T18	29365	0	0	0
T22	1378	0	0	0
T23	8597	0	0	0
T24	72964	0	0	0
T32	0	5	0	0
T33	0	6	0	0
T34	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T79	0	10	0	0
T84	1165	0	0	0
T100	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	396932931	7940	0	0
CgEnOn_A	396932931	5520	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396932931	7940	0	0
T1	30953	1	0	0
T2	128225	1	0	0
T3	238109	1	0	0
T4	6814	1	0	0
T12	2227	1	0	0
T13	106022	1	0	0
T14	2337	10	0	0
T15	3984	1	0	0
T16	1359	1	0	0
T17	5660	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396932931	5520	0	0
T5	136455	0	0	0
T6	0	10	0	0
T7	0	88	0	0
T14	2337	8	0	0
T15	3984	0	0	0
T16	1359	0	0	0
T17	5660	0	0	0
T18	58810	0	0	0
T22	2794	0	0	0
T23	14695	0	0	0
T24	145953	0	0	0
T32	0	5	0	0
T33	0	6	0	0
T34	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T79	0	12	0	0
T84	2354	0	0	0
T100	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204112110	7970	0	0
CgEnOn_A	204112110	5546	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204112110	7970	0	0
T1	15478	1	0	0
T2	64116	1	0	0
T3	119059	1	0	0
T4	3407	1	0	0
T12	1114	1	0	0
T13	58774	1	0	0
T14	1168	12	0	0
T15	1991	1	0	0
T16	680	1	0	0
T17	2830	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204112110	5546	0	0
T5	68231	0	0	0
T6	0	10	0	0
T7	0	88	0	0
T14	1168	10	0	0
T15	1991	0	0	0
T16	680	0	0	0
T17	2830	0	0	0
T18	29406	0	0	0
T22	1397	0	0	0
T23	7348	0	0	0
T24	90260	0	0	0
T32	0	4	0	0
T33	0	5	0	0
T34	0	4	0	0
T37	0	1	0	0
T79	0	10	0	0
T82	0	1	0	0
T84	1177	0	0	0
T100	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Covered	T4,T17,T22
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	425532238	4106	0	0
CgEnOn_A	425532238	4101	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4106	0	0
T3	248038	0	0	0
T4	7099	4	0	0
T6	0	1	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2911	13	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	6	0	0
T127	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4101	0	0
T3	248038	0	0	0
T4	7099	4	0	0
T6	0	1	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2911	13	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	6	0	0
T127	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Covered	T4,T17,T22
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	425532238	4078	0	0
CgEnOn_A	425532238	4073	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4078	0	0
T3	248038	0	0	0
T4	7099	3	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2911	5	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	10	0	0
T127	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4073	0	0
T3	248038	0	0	0
T4	7099	3	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2911	5	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	10	0	0
T127	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Covered	T4,T17,T22
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	425532238	4083	0	0
CgEnOn_A	425532238	4078	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4083	0	0
T3	248038	0	0	0
T4	7099	4	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2911	8	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	9	0	0
T127	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4078	0	0
T3	248038	0	0	0
T4	7099	4	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	2	0	0
T22	2911	8	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	9	0	0
T127	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T6,T32
1	0	Covered	T4,T17,T22
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	425532238	4064	0	0
CgEnOn_A	425532238	4059	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4064	0	0
T3	248038	0	0	0
T4	7099	2	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	3	0	0
T22	2911	6	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	10	0	0
T127	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425532238	4059	0	0
T3	248038	0	0	0
T4	7099	2	0	0
T6	0	2	0	0
T12	2321	0	0	0
T13	152445	0	0	0
T14	2435	0	0	0
T15	4150	0	0	0
T16	1416	0	0	0
T17	5896	3	0	0
T22	2911	6	0	0
T23	15308	0	0	0
T32	0	5	0	0
T33	0	5	0	0
T36	0	1	0	0
T37	0	1	0	0
T98	0	10	0	0
T127	0	10	0	0