Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204085	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

481499

1

T5

11

T6

5

T24

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	201218	1			T5	14		T6	5		T24	80
values[0x0]	229842	1			T5	15		T6	8		T24	32
values[0x1]	254524	1			T5	14		T6	3		T24	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142022	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

543562

1

T5

17

T6

7

T24

66

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2776	1			T4	12		T1	10		T3	46
valid_sources[0x01]	3062	1			T1	5		T178	1		T3	54
valid_sources[0x02]	2345	1			T1	6		T147	4		T3	38
valid_sources[0x03]	2590	1			T1	2		T22	1		T110	1
valid_sources[0x04]	3137	1			T4	2		T110	1		T34	4
valid_sources[0x05]	2611	1			T1	5		T178	1		T3	49
valid_sources[0x06]	2395	1			T29	1		T1	6		T34	1
valid_sources[0x07]	2367	1			T1	4		T178	1		T3	62
valid_sources[0x08]	2176	1			T25	1		T1	8		T3	55
valid_sources[0x09]	2248	1			T4	1		T1	24		T3	48
valid_sources[0x0a]	2505	1			T4	2		T1	19		T179	2
valid_sources[0x0b]	2307	1			T26	2		T1	2		T110	1
valid_sources[0x0c]	2318	1			T1	3		T34	1		T3	51
valid_sources[0x0d]	2714	1			T1	10		T16	3		T3	53
valid_sources[0x0e]	2945	1			T1	5		T147	2		T110	1
valid_sources[0x0f]	2580	1			T29	1		T1	12		T18	3
valid_sources[0x10]	2710	1			T39	61		T1	10		T3	64
valid_sources[0x11]	2629	1			T1	2		T3	56		T75	1
valid_sources[0x12]	2651	1			T4	3		T1	11		T178	1
valid_sources[0x13]	2208	1			T25	1		T4	2		T1	14
valid_sources[0x14]	2519	1			T26	1		T1	11		T22	1
valid_sources[0x15]	2866	1			T4	3		T29	1		T1	7
valid_sources[0x16]	2243	1			T1	14		T17	2		T3	45
valid_sources[0x17]	2552	1			T1	6		T22	2		T178	1
valid_sources[0x18]	2887	1			T4	7		T1	19		T22	1
valid_sources[0x19]	2453	1			T4	17		T1	4		T22	1
valid_sources[0x1a]	2712	1			T4	7		T1	21		T179	1
valid_sources[0x1b]	2595	1			T1	11		T100	5		T110	2
valid_sources[0x1c]	2567	1			T1	11		T18	1		T22	1
valid_sources[0x1d]	2566	1			T4	6		T1	10		T22	1
valid_sources[0x1e]	2536	1			T1	24		T34	2		T3	51
valid_sources[0x1f]	3353	1			T6	1		T4	11		T1	5
valid_sources[0x20]	2587	1			T25	1		T1	14		T34	5
valid_sources[0x21]	2716	1			T1	20		T3	60		T35	1
valid_sources[0x22]	3003	1			T1	6		T34	2		T3	49
valid_sources[0x23]	3033	1			T25	1		T4	3		T29	1
valid_sources[0x24]	3008	1			T26	1		T1	2		T22	3
valid_sources[0x25]	2651	1			T1	22		T110	1		T3	44
valid_sources[0x26]	2453	1			T29	1		T1	13		T178	1
valid_sources[0x27]	2334	1			T17	2		T179	2		T3	44
valid_sources[0x28]	2760	1			T1	10		T3	42		T37	1
valid_sources[0x29]	2294	1			T1	13		T16	2		T18	4
valid_sources[0x2a]	2498	1			T6	1		T1	2		T110	1
valid_sources[0x2b]	3712	1			T1	10		T34	1		T3	38
valid_sources[0x2c]	2713	1			T1	9		T17	1		T18	1
valid_sources[0x2d]	2741	1			T1	19		T22	1		T34	4
valid_sources[0x2e]	2537	1			T25	1		T1	15		T102	16
valid_sources[0x2f]	2479	1			T1	8		T179	1		T3	45
valid_sources[0x30]	2642	1			T22	1		T3	49		T36	5
valid_sources[0x31]	2320	1			T1	7		T16	1		T100	1
valid_sources[0x32]	3433	1			T26	1		T1	18		T34	1
valid_sources[0x33]	2340	1			T26	2		T1	6		T110	1
valid_sources[0x34]	2701	1			T25	1		T1	9		T16	1
valid_sources[0x35]	2290	1			T5	9		T1	12		T34	2
valid_sources[0x36]	2430	1			T26	1		T4	1		T1	10
valid_sources[0x37]	2891	1			T26	1		T4	11		T1	9
valid_sources[0x38]	3525	1			T25	1		T1	23		T22	1
valid_sources[0x39]	2507	1			T25	1		T1	5		T3	38
valid_sources[0x3a]	2407	1			T25	2		T26	2		T4	14
valid_sources[0x3b]	2766	1			T25	1		T26	1		T1	12
valid_sources[0x3c]	3280	1			T1	6		T22	1		T178	1
valid_sources[0x3d]	2681	1			T25	1		T1	8		T34	5
valid_sources[0x3e]	2248	1			T1	18		T3	44		T75	1
valid_sources[0x3f]	2202	1			T1	14		T17	2		T22	1
valid_sources[0x40]	3230	1			T1	5		T3	37		T35	2
valid_sources[0x41]	3235	1			T26	1		T4	5		T1	11
valid_sources[0x42]	2740	1			T1	3		T18	2		T22	1
valid_sources[0x43]	2373	1			T1	3		T34	1		T3	50
valid_sources[0x44]	2265	1			T26	1		T1	13		T3	46
valid_sources[0x45]	2566	1			T4	1		T1	9		T3	61
valid_sources[0x46]	2580	1			T4	1		T1	15		T22	2
valid_sources[0x47]	4880	1			T4	3		T1	10		T147	2
valid_sources[0x48]	2481	1			T1	20		T22	1		T110	1
valid_sources[0x49]	2407	1			T1	15		T34	2		T3	51
valid_sources[0x4a]	2800	1			T26	1		T1	1		T178	1
valid_sources[0x4b]	2759	1			T1	13		T34	2		T3	47
valid_sources[0x4c]	2237	1			T4	7		T34	3		T3	49
valid_sources[0x4d]	2503	1			T25	1		T1	10		T16	1
valid_sources[0x4e]	2750	1			T24	140		T25	1		T1	3
valid_sources[0x4f]	2572	1			T26	1		T4	4		T1	3
valid_sources[0x50]	2883	1			T1	5		T16	1		T34	1
valid_sources[0x51]	2711	1			T1	6		T34	1		T3	62
valid_sources[0x52]	2823	1			T25	1		T1	3		T22	1
valid_sources[0x53]	3047	1			T25	1		T4	16		T1	9
valid_sources[0x54]	2657	1			T1	12		T16	1		T22	1
valid_sources[0x55]	2403	1			T25	2		T26	1		T1	14
valid_sources[0x56]	2616	1			T25	2		T1	5		T34	1
valid_sources[0x57]	2591	1			T1	16		T34	1		T3	46
valid_sources[0x58]	2444	1			T1	18		T110	2		T34	1
valid_sources[0x59]	3363	1			T5	14		T26	1		T1	16
valid_sources[0x5a]	2298	1			T25	2		T1	2		T34	1
valid_sources[0x5b]	2945	1			T25	3		T1	5		T34	3
valid_sources[0x5c]	2740	1			T25	1		T1	7		T100	7
valid_sources[0x5d]	2837	1			T26	1		T4	4		T28	5
valid_sources[0x5e]	2590	1			T1	8		T178	1		T3	42
valid_sources[0x5f]	2938	1			T1	15		T22	1		T3	49
valid_sources[0x60]	2426	1			T1	11		T3	52		T35	3
valid_sources[0x61]	3005	1			T28	44		T1	13		T3	44
valid_sources[0x62]	2483	1			T4	2		T1	13		T3	49
valid_sources[0x63]	2262	1			T1	15		T34	2		T3	45
valid_sources[0x64]	2633	1			T4	10		T1	20		T17	3
valid_sources[0x65]	2852	1			T26	1		T1	6		T22	1
valid_sources[0x66]	3402	1			T1	13		T16	1		T22	2
valid_sources[0x67]	2573	1			T1	8		T3	47		T35	3
valid_sources[0x68]	2445	1			T4	3		T1	3		T110	1
valid_sources[0x69]	2441	1			T25	2		T1	4		T3	48
valid_sources[0x6a]	2197	1			T25	1		T1	6		T22	2
valid_sources[0x6b]	2883	1			T26	2		T1	9		T147	1
valid_sources[0x6c]	2762	1			T4	5		T1	9		T34	2
valid_sources[0x6d]	2332	1			T25	1		T1	18		T110	3
valid_sources[0x6e]	2946	1			T1	17		T147	2		T3	61
valid_sources[0x6f]	2203	1			T1	2		T34	3		T3	58
valid_sources[0x70]	2314	1			T1	14		T16	1		T178	1
valid_sources[0x71]	2877	1			T25	7		T4	1		T1	9
valid_sources[0x72]	2550	1			T1	35		T3	47		T35	1
valid_sources[0x73]	2308	1			T4	13		T1	8		T18	4
valid_sources[0x74]	3428	1			T1	20		T3	38		T35	1
valid_sources[0x75]	2483	1			T26	1		T1	1		T34	1
valid_sources[0x76]	4114	1			T1	16		T22	1		T178	1
valid_sources[0x77]	2745	1			T1	17		T16	4		T178	1
valid_sources[0x78]	2360	1			T4	1		T1	8		T34	3
valid_sources[0x79]	2272	1			T1	7		T147	3		T179	2
valid_sources[0x7a]	2589	1			T1	9		T178	1		T3	56
valid_sources[0x7b]	3164	1			T1	15		T2	418		T3	45
valid_sources[0x7c]	2630	1			T1	9		T147	8		T178	3
valid_sources[0x7d]	2319	1			T1	3		T34	1		T3	55
valid_sources[0x7e]	3258	1			T6	1		T1	12		T34	5
valid_sources[0x7f]	2703	1			T26	1		T1	6		T3	43
valid_sources[0x80]	2320	1			T26	3		T28	19		T1	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

135383

1

T5

7

T6

3

T24

41

values[0x0]

all_enables

biggest_size

185258

1

T5

2

T6

2

T24

8

values[0x1]

all_enables

biggest_size

160858

1

T5

2

T24

8

T25

5