Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T1
0	1	Covered	T1,T102,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T102,T3
1	0	Covered	T7,T32,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	173428593	8623	0	0
GateOpen_A	173428593	15272	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173428593	8623	0	0
T1	0	58	0	0
T3	0	140	0	0
T4	327440	0	0	0
T7	2870	15	0	0
T24	15783	0	0	0
T25	6788	0	0	0
T26	6183	0	0	0
T27	4179	0	0	0
T28	5650	0	0	0
T29	3441	0	0	0
T32	3203	11	0	0
T39	6606	0	0	0
T43	0	11	0	0
T44	0	4	0	0
T102	0	22	0	0
T114	0	4	0	0
T169	0	25	0	0
T170	0	46	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173428593	15272	0	0
T1	0	78	0	0
T4	327440	4	0	0
T6	9107	4	0	0
T7	2870	19	0	0
T16	0	4	0	0
T24	15783	4	0	0
T25	6788	0	0	0
T26	6183	4	0	0
T27	4179	0	0	0
T28	5650	4	0	0
T29	3441	0	0	0
T32	3203	15	0	0
T39	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T1
0	1	Covered	T1,T102,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T102,T3
1	0	Covered	T7,T32,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	18709169	2042	0	0
GateOpen_A	18709169	3702	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18709169	2042	0	0
T1	0	13	0	0
T3	0	33	0	0
T4	35411	0	0	0
T7	303	4	0	0
T24	1736	0	0	0
T25	765	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	681	0	0	0
T29	376	0	0	0
T32	336	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T102	0	4	0	0
T114	0	1	0	0
T169	0	5	0	0
T170	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18709169	3702	0	0
T1	0	18	0	0
T4	35411	1	0	0
T6	1054	1	0	0
T7	303	5	0	0
T16	0	1	0	0
T24	1736	1	0	0
T25	765	0	0	0
T26	716	1	0	0
T27	442	0	0	0
T28	681	1	0	0
T29	376	0	0	0
T32	336	4	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T1
0	1	Covered	T1,T102,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T102,T3
1	0	Covered	T7,T32,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	37418773	2195	0	0
GateOpen_A	37418773	3855	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37418773	2195	0	0
T1	0	16	0	0
T3	0	35	0	0
T4	70822	0	0	0
T7	605	4	0	0
T24	3472	0	0	0
T25	1531	0	0	0
T26	1438	0	0	0
T27	884	0	0	0
T28	1362	0	0	0
T29	752	0	0	0
T32	671	3	0	0
T39	1504	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T102	0	6	0	0
T114	0	1	0	0
T169	0	7	0	0
T170	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37418773	3855	0	0
T1	0	21	0	0
T4	70822	1	0	0
T6	2109	1	0	0
T7	605	5	0	0
T16	0	1	0	0
T24	3472	1	0	0
T25	1531	0	0	0
T26	1438	1	0	0
T27	884	0	0	0
T28	1362	1	0	0
T29	752	0	0	0
T32	671	4	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T1
0	1	Covered	T1,T102,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T102,T3
1	0	Covered	T7,T32,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	76666495	2210	0	0
GateOpen_A	76666495	3874	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76666495	2210	0	0
T1	0	15	0	0
T3	0	35	0	0
T4	141708	0	0	0
T7	1317	4	0	0
T24	7050	0	0	0
T25	2995	0	0	0
T26	2686	0	0	0
T27	1902	0	0	0
T28	2404	0	0	0
T29	1542	0	0	0
T32	1462	3	0	0
T39	2901	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T102	0	6	0	0
T114	0	1	0	0
T169	0	6	0	0
T170	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76666495	3874	0	0
T1	0	20	0	0
T4	141708	1	0	0
T6	3962	1	0	0
T7	1317	5	0	0
T16	0	1	0	0
T24	7050	1	0	0
T25	2995	0	0	0
T26	2686	1	0	0
T27	1902	0	0	0
T28	2404	1	0	0
T29	1542	0	0	0
T32	1462	4	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T32,T1
0	1	Covered	T1,T102,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T102,T3
1	0	Covered	T7,T32,T43
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	40634156	2176	0	0
GateOpen_A	40634156	3841	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40634156	2176	0	0
T1	0	14	0	0
T3	0	37	0	0
T4	79499	0	0	0
T7	645	3	0	0
T24	3525	0	0	0
T25	1497	0	0	0
T26	1343	0	0	0
T27	951	0	0	0
T28	1203	0	0	0
T29	771	0	0	0
T32	734	2	0	0
T39	1450	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T102	0	6	0	0
T114	0	1	0	0
T169	0	7	0	0
T170	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40634156	3841	0	0
T1	0	19	0	0
T4	79499	1	0	0
T6	1982	1	0	0
T7	645	4	0	0
T16	0	1	0	0
T24	3525	1	0	0
T25	1497	0	0	0
T26	1343	1	0	0
T27	951	0	0	0
T28	1203	1	0	0
T29	771	0	0	0
T32	734	3	0	0
T39	0	1	0	0