Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	177708745	29448	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177708745	29448	0	0
T1	505765	890	0	0
T2	998345	622	0	0
T3	0	44	0	0
T9	0	173	0	0
T10	0	584	0	0
T11	0	248	0	0
T12	0	278	0	0
T13	0	114	0	0
T14	0	600	0	0
T15	0	94	0	0
T16	7070	0	0	0
T17	13645	0	0	0
T18	7400	0	0	0
T19	11235	0	0	0
T20	8590	0	0	0
T21	10860	0	0	0
T22	9950	0	0	0
T23	12080	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35541749	4380	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	4380	0	0
T1	101153	115	0	0
T2	199669	79	0	0
T3	0	7	0	0
T9	0	34	0	0
T10	0	76	0	0
T11	0	40	0	0
T12	0	51	0	0
T13	0	18	0	0
T14	0	79	0	0
T15	0	13	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T19	2247	0	0	0
T20	1718	0	0	0
T21	2172	0	0	0
T22	1990	0	0	0
T23	2416	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35541749	4369	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	4369	0	0
T1	101153	112	0	0
T2	199669	90	0	0
T3	0	7	0	0
T9	0	34	0	0
T10	0	85	0	0
T11	0	40	0	0
T12	0	51	0	0
T13	0	18	0	0
T14	0	77	0	0
T15	0	14	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T19	2247	0	0	0
T20	1718	0	0	0
T21	2172	0	0	0
T22	1990	0	0	0
T23	2416	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35541749	5908	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	5908	0	0
T1	101153	181	0	0
T2	199669	121	0	0
T3	0	9	0	0
T9	0	34	0	0
T10	0	118	0	0
T11	0	50	0	0
T12	0	54	0	0
T13	0	22	0	0
T14	0	121	0	0
T15	0	20	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T19	2247	0	0	0
T20	1718	0	0	0
T21	2172	0	0	0
T22	1990	0	0	0
T23	2416	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35541749	5904	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	5904	0	0
T1	101153	179	0	0
T2	199669	125	0	0
T3	0	9	0	0
T9	0	34	0	0
T10	0	115	0	0
T11	0	51	0	0
T12	0	55	0	0
T13	0	23	0	0
T14	0	121	0	0
T15	0	18	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T19	2247	0	0	0
T20	1718	0	0	0
T21	2172	0	0	0
T22	1990	0	0	0
T23	2416	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35541749	8887	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	8887	0	0
T1	101153	303	0	0
T2	199669	207	0	0
T3	0	12	0	0
T9	0	37	0	0
T10	0	190	0	0
T11	0	67	0	0
T12	0	67	0	0
T13	0	33	0	0
T14	0	202	0	0
T15	0	29	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T19	2247	0	0	0
T20	1718	0	0	0
T21	2172	0	0	0
T22	1990	0	0	0
T23	2416	0	0	0