Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T3,T36

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	35541749	32696364	0	0
AllClkBypReqTrue_A	35541749	86140	0	0
IoClkBypReqFalse_A	35541749	32640379	0	2415
IoClkBypReqTrue_A	35541749	137417	0	0
LcClkBypAckFalse_A	35541749	32703763	0	0
LcClkBypAckTrue_A	35541749	78741	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	32696364	0	0
T4	44067	44036	0	0
T5	1955	1647	0	0
T6	1031	911	0	0
T7	1405	1169	0	0
T24	3671	3586	0	0
T25	3119	2906	0	0
T26	2743	2223	0	0
T27	951	814	0	0
T28	2079	1772	0	0
T29	1605	1435	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	86140	0	0
T1	0	622	0	0
T4	44067	0	0	0
T5	1955	281	0	0
T6	1031	74	0	0
T7	1405	0	0	0
T17	0	42	0	0
T19	0	62	0	0
T20	0	29	0	0
T21	0	352	0	0
T24	3671	0	0	0
T25	3119	0	0	0
T26	2743	367	0	0
T27	951	0	0	0
T28	2079	177	0	0
T29	1605	0	0	0
T39	0	94	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	32640379	0	2415
T4	44067	44034	0	3
T5	1955	1449	0	3
T6	1031	938	0	3
T7	1405	1167	0	3
T24	3671	3584	0	3
T25	3119	2254	0	3
T26	2743	2083	0	3
T27	951	775	0	3
T28	2079	1612	0	3
T29	1605	1433	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	137417	0	0
T1	0	1180	0	0
T4	44067	0	0	0
T5	1955	477	0	0
T6	1031	45	0	0
T7	1405	0	0	0
T17	0	436	0	0
T18	0	309	0	0
T24	3671	0	0	0
T25	3119	650	0	0
T26	2743	505	0	0
T27	951	37	0	0
T28	2079	335	0	0
T29	1605	0	0	0
T39	0	493	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	32703763	0	0
T4	44067	44036	0	0
T5	1955	1687	0	0
T6	1031	943	0	0
T7	1405	1169	0	0
T24	3671	3586	0	0
T25	3119	2733	0	0
T26	2743	2355	0	0
T27	951	814	0	0
T28	2079	1752	0	0
T29	1605	1435	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	78741	0	0
T1	0	832	0	0
T4	44067	0	0	0
T5	1955	241	0	0
T6	1031	42	0	0
T7	1405	0	0	0
T17	0	220	0	0
T18	0	72	0	0
T19	0	90	0	0
T24	3671	0	0	0
T25	3119	173	0	0
T26	2743	235	0	0
T27	951	0	0	0
T28	2079	197	0	0
T29	1605	0	0	0
T39	0	229	0	0