Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	339144748	9692	0	0
TransStop_A	339144748	4965	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339144748	9692	0	0
T1	410468	62	0	0
T3	0	82	0	0
T4	662480	0	0	0
T22	0	22	0	0
T24	29376	41	0	0
T25	12480	0	0	0
T26	11192	0	0	0
T27	7924	0	0	0
T28	10016	0	0	0
T29	6424	0	0	0
T32	5932	0	0	0
T39	12088	0	0	0
T44	0	4	0	0
T110	0	12	0	0
T111	0	29	0	0
T112	0	26	0	0
T113	0	30	0	0
T114	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339144748	4965	0	0
T1	410468	33	0	0
T3	0	28	0	0
T4	662480	0	0	0
T9	0	5	0	0
T22	0	9	0	0
T24	29376	24	0	0
T25	12480	0	0	0
T26	11192	0	0	0
T27	7924	0	0	0
T28	10016	0	0	0
T29	6424	0	0	0
T32	5932	0	0	0
T39	12088	0	0	0
T44	0	4	0	0
T110	0	3	0	0
T111	0	7	0	0
T112	0	11	0	0
T113	0	17	0	0
T114	0	4	0	0
T115	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84786187	2420	0	0
TransStop_A	84786187	1239	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	2420	0	0
T1	102617	18	0	0
T3	0	21	0	0
T4	165620	0	0	0
T22	0	6	0	0
T24	7344	10	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T110	0	2	0	0
T111	0	4	0	0
T112	0	7	0	0
T113	0	7	0	0
T114	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	1239	0	0
T1	102617	9	0	0
T3	0	6	0	0
T4	165620	0	0	0
T9	0	3	0	0
T22	0	3	0	0
T24	7344	6	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T112	0	3	0	0
T113	0	4	0	0
T114	0	1	0	0
T115	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84786187	2453	0	0
TransStop_A	84786187	1254	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	2453	0	0
T1	102617	13	0	0
T3	0	20	0	0
T4	165620	0	0	0
T22	0	6	0	0
T24	7344	10	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T110	0	5	0	0
T111	0	9	0	0
T112	0	9	0	0
T113	0	9	0	0
T114	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	1254	0	0
T1	102617	8	0	0
T3	0	8	0	0
T4	165620	0	0	0
T22	0	3	0	0
T24	7344	5	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T110	0	1	0	0
T111	0	2	0	0
T112	0	4	0	0
T113	0	5	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84786187	2387	0	0
TransStop_A	84786187	1234	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	2387	0	0
T1	102617	14	0	0
T3	0	20	0	0
T4	165620	0	0	0
T22	0	8	0	0
T24	7344	9	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T110	0	4	0	0
T111	0	6	0	0
T112	0	5	0	0
T113	0	6	0	0
T114	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	1234	0	0
T1	102617	8	0	0
T3	0	6	0	0
T4	165620	0	0	0
T22	0	3	0	0
T24	7344	5	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	0	3	0	0
T113	0	3	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84786187	2432	0	0
TransStop_A	84786187	1238	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	2432	0	0
T1	102617	17	0	0
T3	0	21	0	0
T4	165620	0	0	0
T22	0	2	0	0
T24	7344	12	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T110	0	1	0	0
T111	0	10	0	0
T112	0	5	0	0
T113	0	8	0	0
T114	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84786187	1238	0	0
T1	102617	8	0	0
T3	0	8	0	0
T4	165620	0	0	0
T9	0	2	0	0
T24	7344	8	0	0
T25	3120	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1606	0	0	0
T32	1483	0	0	0
T39	3022	0	0	0
T44	0	1	0	0
T111	0	4	0	0
T112	0	1	0	0
T113	0	5	0	0
T114	0	1	0	0
T115	0	1	0	0