Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	35541749	2903842	0	56

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	2903842	0	56
T1	101153	108998	0	0
T2	199669	73183	0	1
T3	0	2879	0	0
T9	0	6194	0	0
T10	0	73903	0	0
T11	0	16050	0	0
T12	0	14081	0	0
T13	0	9990	0	0
T14	0	72479	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T19	2247	0	0	0
T20	1718	0	0	0
T21	2172	0	0	0
T22	1990	0	0	0
T23	2416	0	0	0
T30	0	1161	0	1
T31	0	0	0	1
T116	0	0	0	1
T117	0	0	0	1
T118	0	0	0	1
T119	0	0	0	1
T120	0	0	0	1
T121	0	0	0	1
T122	0	0	0	1