Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	36499045	505887	0	0
clk_enables_rd_A	36499045	7009	0	0
clk_hints_rd_A	36499045	6907	0	0
extclk_ctrl_rd_A	36499045	9719	0	0
extclk_ctrl_regwen_rd_A	36499045	5603	0	0
jitter_enable_rd_A	36499045	14501	0	0
jitter_regwen_rd_A	36499045	5480	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	505887	0	0
T3	283818	15989	0	0
T12	0	12924	0	0
T15	0	16817	0	0
T35	174821	0	0	0
T36	55012	0	0	0
T37	12757	0	0	0
T43	1507	0	0	0
T68	0	9849	0	0
T69	0	4372	0	0
T70	0	6636	0	0
T71	0	6051	0	0
T72	0	12390	0	0
T73	0	4367	0	0
T74	0	11026	0	0
T75	2137	0	0	0
T76	2068	0	0	0
T77	1046	0	0	0
T78	1058	0	0	0
T79	2500	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	7009	0	0
T10	935280	4	0	0
T11	190979	0	0	0
T12	0	487	0	0
T45	27584	0	0	0
T49	720	0	0	0
T50	1756	0	0	0
T68	0	233	0	0
T70	0	247	0	0
T71	0	250	0	0
T73	0	173	0	0
T80	100837	0	0	0
T81	14074	0	0	0
T138	0	1	0	0
T139	0	17	0	0
T140	0	3	0	0
T141	0	7	0	0
T142	2618	0	0	0
T143	2093	0	0	0
T144	2609	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	6907	0	0
T10	935280	15	0	0
T11	190979	0	0	0
T12	0	467	0	0
T45	27584	0	0	0
T49	720	0	0	0
T50	1756	0	0	0
T68	0	271	0	0
T70	0	199	0	0
T71	0	245	0	0
T80	100837	0	0	0
T81	14074	0	0	0
T138	0	7	0	0
T139	0	26	0	0
T140	0	2	0	0
T142	2618	0	0	0
T143	2093	0	0	0
T144	2609	0	0	0
T145	0	8	0	0
T146	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	9719	0	0
T1	0	156	0	0
T4	44067	0	0	0
T5	1955	58	0	0
T6	1031	5	0	0
T7	1405	0	0	0
T23	0	46	0	0
T24	3671	0	0	0
T25	3119	62	0	0
T26	2743	42	0	0
T27	951	1	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T75	0	60	0	0
T147	0	69	0	0
T148	0	30	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	5603	0	0
T11	190979	0	0	0
T12	0	379	0	0
T45	27584	0	0	0
T49	720	0	0	0
T50	1756	0	0	0
T51	971	0	0	0
T52	1374	0	0	0
T53	1622	0	0	0
T54	1075	0	0	0
T55	25496	0	0	0
T56	0	16	0	0
T68	0	148	0	0
T70	0	214	0	0
T71	0	233	0	0
T73	0	178	0	0
T81	14074	22	0	0
T108	0	16	0	0
T149	0	20	0	0
T150	0	47	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	14501	0	0
T1	101153	126	0	0
T2	199669	0	0	0
T10	0	235	0	0
T12	0	1153	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T19	2247	0	0	0
T20	1718	0	0	0
T21	2172	0	0	0
T22	1990	0	0	0
T23	2416	0	0	0
T68	0	855	0	0
T70	0	381	0	0
T138	0	100	0	0
T139	0	488	0	0
T140	0	134	0	0
T145	0	84	0	0
T146	0	52	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	5480	0	0
T12	456900	467	0	0
T13	125528	0	0	0
T30	127581	0	0	0
T56	54228	0	0	0
T68	0	193	0	0
T70	0	233	0	0
T71	0	237	0	0
T73	0	233	0	0
T151	0	235	0	0
T152	0	176	0	0
T153	0	214	0	0
T154	0	157	0	0
T155	0	385	0	0
T156	2067	0	0	0
T157	1572	0	0	0
T158	1291	0	0	0
T159	2831	0	0	0
T160	1827	0	0	0
T161	3772	0	0	0