Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	106625247	398	0	0
StatusRise_A	106625247	398	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106625247	398	0	0
T4	132201	0	0	0
T7	4215	9	0	0
T24	11013	0	0	0
T25	9357	0	0	0
T26	8229	0	0	0
T27	2853	0	0	0
T28	6237	0	0	0
T29	4815	0	0	0
T32	4851	8	0	0
T39	9063	0	0	0
T43	0	7	0	0
T50	0	15	0	0
T162	0	13	0	0
T163	0	8	0	0
T164	0	3	0	0
T165	0	4	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106625247	398	0	0
T4	132201	0	0	0
T7	4215	9	0	0
T24	11013	0	0	0
T25	9357	0	0	0
T26	8229	0	0	0
T27	2853	0	0	0
T28	6237	0	0	0
T29	4815	0	0	0
T32	4851	8	0	0
T39	9063	0	0	0
T43	0	7	0	0
T50	0	15	0	0
T162	0	13	0	0
T163	0	8	0	0
T164	0	3	0	0
T165	0	4	0	0
T166	0	3	0	0
T167	0	3	0	0
T168	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35541749	129	0	0
StatusRise_A	35541749	129	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	129	0	0
T4	44067	0	0	0
T7	1405	2	0	0
T24	3671	0	0	0
T25	3119	0	0	0
T26	2743	0	0	0
T27	951	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	129	0	0
T4	44067	0	0	0
T7	1405	2	0	0
T24	3671	0	0	0
T25	3119	0	0	0
T26	2743	0	0	0
T27	951	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35541749	133	0	0
StatusRise_A	35541749	133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	133	0	0
T4	44067	0	0	0
T7	1405	4	0	0
T24	3671	0	0	0
T25	3119	0	0	0
T26	2743	0	0	0
T27	951	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	3	0	0
T39	3021	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	133	0	0
T4	44067	0	0	0
T7	1405	4	0	0
T24	3671	0	0	0
T25	3119	0	0	0
T26	2743	0	0	0
T27	951	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	3	0	0
T39	3021	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35541749	136	0	0
StatusRise_A	35541749	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	136	0	0
T4	44067	0	0	0
T7	1405	3	0	0
T24	3671	0	0	0
T25	3119	0	0	0
T26	2743	0	0	0
T27	951	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	2	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35541749	136	0	0
T4	44067	0	0	0
T7	1405	3	0	0
T24	3671	0	0	0
T25	3119	0	0	0
T26	2743	0	0	0
T27	951	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	2	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0