Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	892985870	34118	0	0
CgEnOn_A	892985870	24668	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892985870	34118	0	0
T1	0	18	0	0
T4	1719412	3	0	0
T5	18336	3	0	0
T6	9106	3	0	0
T7	14234	37	0	0
T22	0	6	0	0
T24	79092	13	0	0
T25	33814	3	0	0
T26	30586	3	0	0
T27	21124	3	0	0
T28	27678	3	0	0
T29	17260	3	0	0
T32	12761	18	0	0
T39	26233	0	0	0
T43	0	17	0	0
T50	0	25	0	0
T68	0	5	0	0
T73	0	5	0	0
T162	0	25	0	0
T163	0	10	0	0
T164	0	5	0	0
T165	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	892985870	24668	0	0
T1	0	77	0	0
T3	0	173	0	0
T4	1719412	0	0	0
T7	14234	34	0	0
T22	0	6	0	0
T24	79092	10	0	0
T25	33814	0	0	0
T26	30586	0	0	0
T27	21124	0	0	0
T28	27678	0	0	0
T29	17260	0	0	0
T32	15960	27	0	0
T39	32838	0	0	0
T43	0	26	0	0
T44	0	3	0	0
T50	0	25	0	0
T68	0	5	0	0
T73	0	5	0	0
T102	0	37	0	0
T110	0	2	0	0
T111	0	4	0	0
T114	0	3	0	0
T162	0	25	0	0
T163	0	10	0	0
T164	0	5	0	0
T165	0	5	0	0
T169	0	24	0	0
T170	0	48	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	37418350	147	0	0
CgEnOn_A	37418350	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37418350	147	0	0
T4	70821	0	0	0
T7	605	4	0	0
T24	3471	0	0	0
T25	1530	0	0	0
T26	1438	0	0	0
T27	883	0	0	0
T28	1361	0	0	0
T29	751	0	0	0
T32	670	3	0	0
T39	1503	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37418350	147	0	0
T4	70821	0	0	0
T7	605	4	0	0
T24	3471	0	0	0
T25	1530	0	0	0
T26	1438	0	0	0
T27	883	0	0	0
T28	1361	0	0	0
T29	751	0	0	0
T32	670	3	0	0
T39	1503	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18708777	147	0	0
CgEnOn_A	18708777	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	147	0	0
T4	35411	0	0	0
T7	302	4	0	0
T24	1736	0	0	0
T25	764	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	680	0	0	0
T29	376	0	0	0
T32	335	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	147	0	0
T4	35411	0	0	0
T7	302	4	0	0
T24	1736	0	0	0
T25	764	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	680	0	0	0
T29	376	0	0	0
T32	335	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18708777	147	0	0
CgEnOn_A	18708777	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	147	0	0
T4	35411	0	0	0
T7	302	4	0	0
T24	1736	0	0	0
T25	764	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	680	0	0	0
T29	376	0	0	0
T32	335	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	147	0	0
T4	35411	0	0	0
T7	302	4	0	0
T24	1736	0	0	0
T25	764	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	680	0	0	0
T29	376	0	0	0
T32	335	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18708777	147	0	0
CgEnOn_A	18708777	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	147	0	0
T4	35411	0	0	0
T7	302	4	0	0
T24	1736	0	0	0
T25	764	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	680	0	0	0
T29	376	0	0	0
T32	335	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	147	0	0
T4	35411	0	0	0
T7	302	4	0	0
T24	1736	0	0	0
T25	764	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	680	0	0	0
T29	376	0	0	0
T32	335	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76666058	147	0	0
CgEnOn_A	76666058	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76666058	147	0	0
T4	141708	0	0	0
T7	1316	4	0	0
T24	7049	0	0	0
T25	2995	0	0	0
T26	2686	0	0	0
T27	1901	0	0	0
T28	2404	0	0	0
T29	1541	0	0	0
T32	1461	3	0	0
T39	2901	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76666058	136	0	0
T4	141708	0	0	0
T7	1316	4	0	0
T24	7049	0	0	0
T25	2995	0	0	0
T26	2686	0	0	0
T27	1901	0	0	0
T28	2404	0	0	0
T29	1541	0	0	0
T32	1461	3	0	0
T39	2901	0	0	0
T43	0	3	0	0
T50	0	5	0	0
T68	0	1	0	0
T73	0	1	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84785747	138	0	0
CgEnOn_A	84785747	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	138	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T15	0	1	0	0
T24	7343	0	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	130	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T24	7343	0	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84785747	138	0	0
CgEnOn_A	84785747	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	138	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T15	0	1	0	0
T24	7343	0	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	130	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T24	7343	0	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40633732	142	0	0
CgEnOn_A	40633732	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40633732	142	0	0
T4	79498	0	0	0
T7	644	3	0	0
T24	3525	0	0	0
T25	1497	0	0	0
T26	1343	0	0	0
T27	951	0	0	0
T28	1202	0	0	0
T29	771	0	0	0
T32	733	2	0	0
T39	1450	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T68	0	1	0	0
T152	0	1	0	0
T162	0	4	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40633732	136	0	0
T4	79498	0	0	0
T7	644	3	0	0
T24	3525	0	0	0
T25	1497	0	0	0
T26	1343	0	0	0
T27	951	0	0	0
T28	1202	0	0	0
T29	771	0	0	0
T32	733	2	0	0
T39	1450	0	0	0
T43	0	2	0	0
T50	0	5	0	0
T162	0	4	0	0
T163	0	3	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T43
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18708777	5665	0	0
CgEnOn_A	18708777	3325	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	5665	0	0
T4	35411	1	0	0
T5	2200	1	0	0
T6	1054	1	0	0
T7	302	5	0	0
T24	1736	1	0	0
T25	764	1	0	0
T26	716	1	0	0
T27	442	1	0	0
T28	680	1	0	0
T29	376	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18708777	3325	0	0
T1	0	19	0	0
T3	0	51	0	0
T4	35411	0	0	0
T7	302	4	0	0
T24	1736	0	0	0
T25	764	0	0	0
T26	716	0	0	0
T27	442	0	0	0
T28	680	0	0	0
T29	376	0	0	0
T32	335	3	0	0
T39	751	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T102	0	12	0	0
T114	0	1	0	0
T169	0	8	0	0
T170	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T43
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	37418350	5681	0	0
CgEnOn_A	37418350	3341	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37418350	5681	0	0
T4	70821	1	0	0
T5	4402	1	0	0
T6	2109	1	0	0
T7	605	5	0	0
T24	3471	1	0	0
T25	1530	1	0	0
T26	1438	1	0	0
T27	883	1	0	0
T28	1361	1	0	0
T29	751	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37418350	3341	0	0
T1	0	20	0	0
T3	0	51	0	0
T4	70821	0	0	0
T7	605	4	0	0
T24	3471	0	0	0
T25	1530	0	0	0
T26	1438	0	0	0
T27	883	0	0	0
T28	1361	0	0	0
T29	751	0	0	0
T32	670	3	0	0
T39	1503	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T102	0	11	0	0
T114	0	1	0	0
T169	0	8	0	0
T170	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T43
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76666058	5707	0	0
CgEnOn_A	76666058	3356	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76666058	5707	0	0
T4	141708	1	0	0
T5	7823	1	0	0
T6	3962	1	0	0
T7	1316	5	0	0
T24	7049	1	0	0
T25	2995	1	0	0
T26	2686	1	0	0
T27	1901	1	0	0
T28	2404	1	0	0
T29	1541	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76666058	3356	0	0
T1	0	20	0	0
T3	0	50	0	0
T4	141708	0	0	0
T7	1316	4	0	0
T24	7049	0	0	0
T25	2995	0	0	0
T26	2686	0	0	0
T27	1901	0	0	0
T28	2404	0	0	0
T29	1541	0	0	0
T32	1461	3	0	0
T39	2901	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T102	0	14	0	0
T114	0	1	0	0
T169	0	8	0	0
T170	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T43
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40633732	5668	0	0
CgEnOn_A	40633732	3314	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40633732	5668	0	0
T4	79498	1	0	0
T5	3911	1	0	0
T6	1981	1	0	0
T7	644	4	0	0
T24	3525	1	0	0
T25	1497	1	0	0
T26	1343	1	0	0
T27	951	1	0	0
T28	1202	1	0	0
T29	771	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40633732	3314	0	0
T1	0	19	0	0
T3	0	53	0	0
T4	79498	0	0	0
T7	644	3	0	0
T24	3525	0	0	0
T25	1497	0	0	0
T26	1343	0	0	0
T27	951	0	0	0
T28	1202	0	0	0
T29	771	0	0	0
T32	733	2	0	0
T39	1450	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T102	0	12	0	0
T114	0	1	0	0
T169	0	9	0	0
T170	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Covered	T24,T1,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84785747	2558	0	0
CgEnOn_A	84785747	2550	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2558	0	0
T1	0	18	0	0
T3	0	21	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	6	0	0
T24	7343	10	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	2	0	0
T111	0	4	0	0
T112	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2550	0	0
T1	0	18	0	0
T3	0	21	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	6	0	0
T24	7343	10	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	2	0	0
T111	0	4	0	0
T112	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Covered	T24,T1,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84785747	2591	0	0
CgEnOn_A	84785747	2583	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2591	0	0
T1	0	13	0	0
T3	0	20	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	6	0	0
T24	7343	10	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	5	0	0
T111	0	9	0	0
T112	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2583	0	0
T1	0	13	0	0
T3	0	20	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	6	0	0
T24	7343	10	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	5	0	0
T111	0	9	0	0
T112	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Covered	T24,T1,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84785747	2525	0	0
CgEnOn_A	84785747	2517	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2525	0	0
T1	0	14	0	0
T3	0	20	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	8	0	0
T24	7343	9	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	4	0	0
T111	0	6	0	0
T112	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2517	0	0
T1	0	14	0	0
T3	0	20	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	8	0	0
T24	7343	9	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	4	0	0
T111	0	6	0	0
T112	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T32,T1
1	0	Covered	T24,T1,T22
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84785747	2570	0	0
CgEnOn_A	84785747	2562	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2570	0	0
T1	0	17	0	0
T3	0	21	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	2	0	0
T24	7343	12	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	1	0	0
T111	0	10	0	0
T112	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84785747	2562	0	0
T1	0	17	0	0
T3	0	21	0	0
T4	165619	0	0	0
T7	1316	2	0	0
T22	0	2	0	0
T24	7343	12	0	0
T25	3119	0	0	0
T26	2798	0	0	0
T27	1981	0	0	0
T28	2504	0	0	0
T29	1605	0	0	0
T32	1482	3	0	0
T39	3021	0	0	0
T43	0	2	0	0
T110	0	1	0	0
T111	0	10	0	0
T112	0	5	0	0