Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	192745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

460006

1

T10

9

T11

27

T7

4406

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	191672	1			T10	11		T11	42		T7	1354
values[0x0]	218367	1			T10	11		T11	20		T7	1860
values[0x1]	242712	1			T10	12		T11	19		T7	2138

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	133345	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

519406

1

T10

12

T11

35

T7

4777

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2732	1			T11	1		T7	40		T33	1
valid_sources[0x01]	2575	1			T7	13		T8	1		T34	1
valid_sources[0x02]	2296	1			T7	22		T38	1		T37	4
valid_sources[0x03]	2157	1			T11	1		T7	6		T41	1
valid_sources[0x04]	3634	1			T7	22		T42	4		T44	1
valid_sources[0x05]	2417	1			T11	1		T7	16		T32	3
valid_sources[0x06]	2588	1			T7	62		T8	1		T37	12
valid_sources[0x07]	2326	1			T11	1		T41	1		T1	2
valid_sources[0x08]	2666	1			T7	13		T41	1		T84	2
valid_sources[0x09]	2527	1			T11	1		T7	27		T8	2
valid_sources[0x0a]	2697	1			T7	16		T34	1		T49	1
valid_sources[0x0b]	2459	1			T10	1		T7	11		T50	1
valid_sources[0x0c]	2494	1			T7	2		T87	1		T167	1
valid_sources[0x0d]	2450	1			T10	1		T7	16		T37	7
valid_sources[0x0e]	2448	1			T7	13		T32	2		T87	1
valid_sources[0x0f]	2859	1			T7	25		T34	1		T38	2
valid_sources[0x10]	2433	1			T11	2		T7	17		T45	3
valid_sources[0x11]	2062	1			T7	3		T34	1		T41	1
valid_sources[0x12]	3141	1			T7	43		T8	1		T38	1
valid_sources[0x13]	3311	1			T7	1		T8	1		T33	2
valid_sources[0x14]	2403	1			T7	2		T8	2		T33	4
valid_sources[0x15]	2873	1			T7	3		T8	1		T167	1
valid_sources[0x16]	2043	1			T10	1		T7	14		T40	3
valid_sources[0x17]	2174	1			T11	4		T7	10		T8	1
valid_sources[0x18]	2235	1			T7	31		T33	1		T42	6
valid_sources[0x19]	2799	1			T11	1		T7	45		T85	1
valid_sources[0x1a]	2406	1			T7	1		T41	1		T42	3
valid_sources[0x1b]	2485	1			T7	8		T38	1		T50	1
valid_sources[0x1c]	2787	1			T7	15		T8	1		T39	2
valid_sources[0x1d]	2804	1			T11	1		T7	23		T50	1
valid_sources[0x1e]	2500	1			T7	20		T45	2		T1	2
valid_sources[0x1f]	2760	1			T7	3		T40	2		T44	2
valid_sources[0x20]	2797	1			T7	31		T8	2		T33	2
valid_sources[0x21]	2380	1			T11	1		T7	38		T38	4
valid_sources[0x22]	2490	1			T11	1		T7	7		T8	1
valid_sources[0x23]	2458	1			T11	1		T7	28		T50	2
valid_sources[0x24]	2489	1			T10	1		T7	8		T8	2
valid_sources[0x25]	2383	1			T7	21		T39	2		T45	1
valid_sources[0x26]	2836	1			T7	10		T8	3		T37	16
valid_sources[0x27]	2921	1			T7	18		T33	2		T40	1
valid_sources[0x28]	2297	1			T10	1		T7	16		T8	2
valid_sources[0x29]	2822	1			T7	54		T32	1		T40	2
valid_sources[0x2a]	2246	1			T11	1		T7	1		T194	1
valid_sources[0x2b]	2373	1			T7	69		T8	1		T39	1
valid_sources[0x2c]	2706	1			T11	1		T7	35		T41	1
valid_sources[0x2d]	3987	1			T11	1		T7	73		T42	3
valid_sources[0x2e]	2365	1			T7	4		T50	3		T42	3
valid_sources[0x2f]	2124	1			T7	15		T8	1		T40	5
valid_sources[0x30]	2126	1			T7	16		T50	1		T44	2
valid_sources[0x31]	1863	1			T11	1		T7	10		T34	1
valid_sources[0x32]	2356	1			T7	15		T38	1		T167	5
valid_sources[0x33]	1992	1			T7	9		T8	3		T50	1
valid_sources[0x34]	2084	1			T7	33		T8	1		T194	4
valid_sources[0x35]	2237	1			T7	1		T37	9		T42	9
valid_sources[0x36]	2520	1			T7	10		T34	2		T38	2
valid_sources[0x37]	2504	1			T7	33		T32	1		T8	1
valid_sources[0x38]	2441	1			T11	1		T7	22		T45	1
valid_sources[0x39]	2489	1			T7	13		T8	1		T41	1
valid_sources[0x3a]	2277	1			T11	1		T7	11		T32	1
valid_sources[0x3b]	2569	1			T7	9		T50	1		T41	1
valid_sources[0x3c]	2326	1			T11	3		T7	34		T49	1
valid_sources[0x3d]	2366	1			T7	9		T33	1		T50	1
valid_sources[0x3e]	2394	1			T11	1		T7	14		T45	1
valid_sources[0x3f]	2597	1			T7	10		T85	1		T45	3
valid_sources[0x40]	2765	1			T7	29		T8	1		T50	1
valid_sources[0x41]	2325	1			T7	8		T41	1		T45	1
valid_sources[0x42]	2358	1			T7	12		T32	1		T8	2
valid_sources[0x43]	2913	1			T11	1		T7	118		T50	1
valid_sources[0x44]	2526	1			T11	1		T7	26		T41	1
valid_sources[0x45]	2682	1			T7	37		T32	1		T8	1
valid_sources[0x46]	2475	1			T7	6		T33	1		T37	25
valid_sources[0x47]	2882	1			T7	16		T41	1		T84	5
valid_sources[0x48]	2729	1			T7	12		T5	1		T45	1
valid_sources[0x49]	2112	1			T7	27		T38	3		T45	4
valid_sources[0x4a]	2459	1			T11	1		T7	4		T45	3
valid_sources[0x4b]	2444	1			T11	1		T7	14		T8	1
valid_sources[0x4c]	2838	1			T7	28		T8	2		T38	3
valid_sources[0x4d]	2798	1			T10	1		T11	1		T7	9
valid_sources[0x4e]	1960	1			T7	13		T8	2		T42	4
valid_sources[0x4f]	2364	1			T11	1		T7	3		T8	2
valid_sources[0x50]	2664	1			T10	1		T7	6		T37	15
valid_sources[0x51]	2778	1			T7	3		T37	9		T45	2
valid_sources[0x52]	2316	1			T7	28		T8	2		T38	1
valid_sources[0x53]	2292	1			T7	34		T33	3		T44	3
valid_sources[0x54]	2513	1			T7	26		T32	1		T49	1
valid_sources[0x55]	2255	1			T7	60		T50	1		T29	5
valid_sources[0x56]	2284	1			T7	4		T8	1		T167	3
valid_sources[0x57]	2488	1			T33	1		T85	1		T167	1
valid_sources[0x58]	2487	1			T7	3		T8	1		T45	1
valid_sources[0x59]	2367	1			T7	11		T8	1		T38	2
valid_sources[0x5a]	3196	1			T11	1		T7	16		T8	1
valid_sources[0x5b]	2854	1			T10	1		T7	29		T34	1
valid_sources[0x5c]	2436	1			T7	23		T33	1		T45	2
valid_sources[0x5d]	2419	1			T11	1		T7	5		T41	1
valid_sources[0x5e]	2330	1			T7	5		T8	1		T44	1
valid_sources[0x5f]	3028	1			T7	21		T8	1		T50	1
valid_sources[0x60]	3298	1			T7	87		T50	1		T44	3
valid_sources[0x61]	2407	1			T7	6		T33	2		T5	2
valid_sources[0x62]	2553	1			T11	1		T7	28		T32	1
valid_sources[0x63]	2112	1			T7	7		T8	1		T37	19
valid_sources[0x64]	2414	1			T7	31		T33	1		T115	1
valid_sources[0x65]	2567	1			T11	1		T7	17		T38	6
valid_sources[0x66]	2650	1			T7	23		T8	1		T34	1
valid_sources[0x67]	3197	1			T7	1		T44	4		T45	1
valid_sources[0x68]	2174	1			T7	36		T34	1		T87	1
valid_sources[0x69]	2608	1			T11	1		T7	43		T32	1
valid_sources[0x6a]	2447	1			T10	2		T7	10		T33	1
valid_sources[0x6b]	2640	1			T7	14		T8	1		T50	1
valid_sources[0x6c]	2566	1			T7	5		T37	13		T45	1
valid_sources[0x6d]	3326	1			T7	54		T8	1		T41	1
valid_sources[0x6e]	2476	1			T11	1		T7	4		T8	1
valid_sources[0x6f]	3011	1			T7	5		T32	2		T37	17
valid_sources[0x70]	1970	1			T10	2		T7	65		T8	2
valid_sources[0x71]	3221	1			T7	54		T33	2		T40	5
valid_sources[0x72]	2368	1			T11	1		T7	23		T45	5
valid_sources[0x73]	2842	1			T7	2		T38	5		T40	2
valid_sources[0x74]	2582	1			T10	1		T7	25		T42	9
valid_sources[0x75]	2637	1			T7	62		T38	3		T41	2
valid_sources[0x76]	2462	1			T7	7		T8	2		T9	162
valid_sources[0x77]	2573	1			T11	1		T7	4		T8	3
valid_sources[0x78]	2511	1			T7	27		T50	4		T87	1
valid_sources[0x79]	2847	1			T11	1		T7	2		T41	1
valid_sources[0x7a]	3470	1			T11	1		T7	15		T38	2
valid_sources[0x7b]	2162	1			T7	7		T50	2		T45	1
valid_sources[0x7c]	3005	1			T11	1		T7	45		T38	1
valid_sources[0x7d]	2348	1			T45	1		T1	1		T26	4
valid_sources[0x7e]	2427	1			T7	15		T8	2		T42	2
valid_sources[0x7f]	2678	1			T7	3		T8	2		T33	1
valid_sources[0x80]	2325	1			T7	30		T33	2		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

129090

1

T10

5

T11

14

T7

1120

values[0x0]

all_enables

biggest_size

176956

1

T10

4

T11

8

T7

1690

values[0x1]

all_enables

biggest_size

153960

1

T11

5

T7

1596

T32

2